View P90CL301_163523.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
DATA SHEET
P90CL301BFH (C100) Low voltage 16-bit microcontroller
Preliminary specification File under Integrated Circuits, IC17 1996 Dec 11
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
CONTENTS 1 2 2.1 3 4 5 5.1 5.2 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 8 8.1 8.2 8.3 9 10 10.1 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 FEATURES DESCRIPTION Compatibility between P90CL301AFH and P90CL301BFH ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pinning Pin description SYSTEM CONTROL Memory organization Programmable chip-select Dynamic bus port sizing System Control Register (SYSCON) Reset operation Clock generation Interrupt controller Power reduction modes CPU FUNCTIONAL DESCRIPTION General Programming model and data organization Processing states and exception processing Tracing Stack format CPU interrupt processing Bus arbitration PORTS Port P Control Register (PCON) Port SP Ports schematics 8051 PERIPHERAL BUS ON-CHIP PERIPHERAL FUNCTIONS Peripheral interrupt control TIMERS Timer array Timebase Channel function Pin parallel functions for the timer Timer Control Registers Timer Status Register Watchdog Timer 13.1 13.2 14 14.1 15 15.1 15.2 16 17 18 19 20 21 22 23 24 25 26 26.1 27 28 29 29.1 29.2 29.3 29.4 30 31 32 12 12.1 12.2 12.3 12.4 12.5 13
P90CL301BFH (C100)
SERIAL INTERFACES UART interface Baud rate generator UART queue I2C-bus interface Serial Control Register (SCON) PULSE WIDTH MODULATION OUTPUTS (PWM) Prescaler PWM Register (PWMP) PWM Data Registers (PWM0 and PWM1) ANALOG-TO-DIGITAL CONVERTER (ADC) ADC Control Register (ADCON) ON-BOARD TEST CONCEPT ONCE mode Test ROM ON-CHIP RAM REGISTER MAPPING LIMITING VALUES DC CHARACTERISTICS ADC CHARACTERISTICS AC CHARACTERISTICS 8051 BUS TIMING TIMING DIAGRAMS CLOCK TIMING PIN STATES IN VARIOUS MODES INSTRUCTION SET AND ADDRESSING MODES Addressing modes INSTRUCTION TIMING PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1996 Dec 11
2
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
1 FEATURES
P90CL301BFH (C100)
* 512 bytes RAM on-chip * On-Circuit Emulation (ONCE) mode and internal Test-ROM (256 bytes) for on-board testing * 80-pin LQFP package * Temperature range -40 to +85 C * 0.5 micron CMOS low voltage technology. 2 DESCRIPTION
* Fully 68000 software compatible * Static design with 32-bit internal structure * Power saving modes: Power-down, Standby and Idle mode * External clock input: 27 MHz at 2.7 V * Single supply voltage of 2.7 to 3.6 V; down to 1.8 V for RAM retention * 68000 compatible bus interface * Intel 8051 compatible bus interface * 16 Mbytes program/data address range * 8 programmable chip-selects * Dynamic bus sizing, 16 or 8-bit memory bus port size * 56 powerful instruction types: - 5 basic data types, and - 14 addressing modes * 7 programmable interrupt inputs: - a Non-Maskable Interrupt input (NMIN) - 14 auto-vectored interrupts and 7 interrupt priority levels * 24 port pins (multiplexed with other functions) * 2 UART serial interfaces; an independent baud rate generator with two programmable outputs (UART0 and UART1) * UART queue with maximum 256 bytes * I2C-bus serial interface 100 kbaud * 2 timer arrays including: - two 16-bit reference counters and 8-bit programmable prescalers - six 16-bit match/capture registers with equality comparators * Watchdog Timer with 21-bit resolution * Two 8-bit Pulse Width Modulation (PWM) outputs with 8-bit prescaler * Four 8-bit Analog-to-Digital Converter (ADC) inputs with Power-down mode 3 ORDERING INFORMATION
The P90CL301BFH is a highly integrated low-voltage 16/32-bit microcontroller especially suitable for digital mobile systems such as GSM, DCS1900, IS54/95 and other applications requiring low voltage, low power consumption and high computing power. It is fully software compatible with the 68000. The P90CL301BFH optimizes system cost by providing both standard as well as advanced peripheral functions on-chip. The P90CL301BFH has a full static design and special Idle, Standby and Power-down modes which allow further reduction of the total system power consumption. An 80-pin LQFP package dramatically reduces system size requirements. 2.1 Compatibility between P90CL301AFH and P90CL301BFH
For functional compatibility between P90CL301AFH (SAC1 process) and P90CL301BFH (C100 process), the following points should be considered when using the P90CL301BFH: * Wake-up; to wake-up the processor from Power-down mode via the activation of an external SPn pin, it is necessary to enable the interrupt mode first by setting the corresponding bit in the SPCON register. * SYSCON register; for the P90CL301AFH bits 11 to 15 in the SYSCON register should not be set in order to keep additional functionality in the P90CL301BFH inactive.
PACKAGE TYPE NUMBER NAME P90CL301BFH LQFP80 DESCRIPTION plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm 3 VERSION SOT315-1
TEMPERATURE RANGE (C) -40 to +85
1996 Dec 11
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
4 BLOCK DIAGRAM
P90CL301BFH (C100)
handbook, full pagewidth
CS0 to CS2 CS3 to CS6 CSBT/ONCE
D15 to D0
HALT
CPU 68000 A31 to A0
BUS INTERFACE
A23 to A1 AS LDS UDS R/W D15 to D0 DTACK BSIZE
WATCHDOG TIMER
2 x 16-BIT TIMERS 6 CHANNELS
CP0 to CP5
RESET RESET RESETIN
BAUD RATE GENERATOR
TX0 UART0 RX0 SYSTEM CTRL TX1 UART1 RX1 XTAL1 CLOCK PWM0 PWM PWM1 INT0 to INT6 INTERRUPTS NMIN I2C-BUS INTERFACE SCL SDA VDDA VSSA ADC0 to ADC3 Vref(A) PORT P0 to P15 address bus A31 to A0 TEST ROM data bus D15 to D0
MGD780
RAM 512 BYTES
8-BIT ADC
SP0 to SP7
UART QUEUE
VDD1 VDD2 VDD3 VSS1 VSS2
Fig.1 P90CL301BFH block diagram.
1996 Dec 11
4
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
5 5.1 PINNING INFORMATION Pinning
P90CL301BFH (C100)
64 P12/ADC0
63 P13/ADC1
62 P14/ADC2
66 RESETIN
80 LDS [DS]
ndbook, full pagewidth
79 R/W / TROM
78 DTACK
75 D10/P2
74 D11/P3
73 D12/P4
72 D13/P5
71 D14/P6
70 D15/P7
67 RESET
61 Vref(A) 60 P15/ADC3 59 VDDA 58 BSIZE 57 P11/SDA 56 P10/SCL 55 P9/PWM1 (CP1) 54 P8/PWM0 (CP0) 53 SP0/RX1/INT0 52 SP1/TX1/INT1 (CLK0) 51 VSS2 50 SP2/RX0/INT2 (CP2) 49 SP3/TX0/INT3 (CP3) 48 SP4/INT4 (CP4) 47 SP5/INT5 (CP5) 46 SP6/INT6 (CLK1) 45 NMIN/SP7 44 CS0/FC0 43 CS1/FC1 42 CS2/FC2 41 CS3/ALE 40 CS4/RD
MGD773
77 D8/P0
76 D9/P1
AS D7 D6 D5 D4 D3 D2 D1 D0 VDD3 XTAL1 VSS1 UDS/A0/AD0 A1/AD1 A2/AD2 A3/AD3 A4/AD4 A5/AD5 A6/AD6 A7/AD7
1 2 3 4 5 6 7 8 9 10
P90CL301BFH
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 CSBT/ONCE 39 CS5/WR
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
VDD2
A19/PCS0
A20/PCS1
A21/PCS2
A22/PCS3
65 VSSA
69 VDD1
68 HALT
Fig.2 Pinning diagram of the P90CL301BFH (LQFP80).
1996 Dec 11
5
CS6/A23
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
5.2 Pin description Pin description for the P90CL301BFH PIN 1 2 to 9 10 11 12 13 address strobe lower 8-bits of data bus supply voltage; third pin external clock input ground; first pin
P90CL301BFH (C100)
Table 1
SYMBOL(1) AS D7 to D0 VDD3 XTAL1 VSS1 UDS/A0/AD0 A1/AD1 to A7/AD7 A8 to A18 VDD2 A19/PCS0 to A22/PCS3 CS6/A23 CSBT/ONCE CS5/WR CS4/RD CS3/ALE CS2/FC2 to CS0/FC0 NMIN/SP7 SP6/INT6 (CLK1) SP5/INT5 (CP5) SP4/INT4 (CP4) SP3/TX0/INT3 (CP3) SP2/RX0/INT2 (CP2) VSS2 SP1/TX1/INT1 (CLK0) SP0/RX1/INT0 P8/PWM0 (CP0) P9/PWM1 (CP1) P10/SCL P11/SDA BSIZE VDDA P15/ADC3 Vref(A) P14/ADC2 to P12/ADC0 VSSA RESETIN 1996 Dec 11
DESCRIPTION
upper data strobe or LSB of address bus or LSB of 8051 address/data
14 to 20 lower 7-bits of the 68000 address bus or lower 7-bits of the 8051 bus 21 to 31 upper 11-bits of the 68000 address bus 32 37 38 39 40 41 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 65 66 supply voltage; second pin chip-select 6 or address bit 23 chip-select boot or ONCE mode forced input chip-select 5 or 8051 bus write strobe chip-select 4 or 8051 bus read strobe chip-select 3 or 8051 bus address latch Non-Maskable Interrupt or second port pin (bit 7) second port pin (bit 6) external interrupt input 6 (external clock of timer 1) second port pin (bit 5) or external interrupt input 5 (Timer 1 capture input 5) second port pin (bit 4) or external interrupt input 4 (Timer 1 capture input 4) second port pin (bit 3) or Transmit data for UART0 or external interrupt input 3 (Timer 1 capture input 3) second port pin (bit 2) or Receive data for UART0 or external interrupt input 2 (Timer 0 capture input 2) ground; second pin second port pin (bit 1) or transmit data for UART1 or external interrupt input 1 (external clock of Timer 0) second port pin (bit 0) or receive data for UART1 or external interrupt input 0 port pin (bit 8) or PWM0 output (Timer 0 capture input 0) port pin (bit 9) or PWM1 output (Timer 0 capture input 1) port pin (bit 10) or I2C-bus Serial Clock. port pin (bit 11) or I2C-bus Serial Data. data bus size; 8 or 16-bit wide ADC supply voltage port pin (bit 15) or ADC input 3 ADC reference voltage ADC ground external Power-on-reset input 6 33 to 36 upper 4-bits of the address bus or 8051 bus chip-select
42 to 44 chip-select 2 to 0 or data bus function code 2 to 0
62 to 64 port pin (bit 14 to bit 12) or ADC inputs 2 to 0
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
SYMBOL(1) RESET HALT VDD1 D15/P7 to D8/P0 DTACK R/W / TROM LDS [DS] Note
PIN 67 68 69 reset (bidirectional) halt (bidirectional) supply voltage; first pin
DESCRIPTION
70 to 77 upper 8-bits of data bus or 8-bit Port 7 to Port 0; the selected function after reset is defined by pin BSIZE 78 79 80 data transfer acknowledge read/write bus control or Test-ROM forced input lower data strobe [word data strobe]
1. The following notation is used to describe the multiple pin definitions: a) Function1/Function2/Function3: multiplexed functions on the same pin. During and after reset the Function1 is selected. b) Function1 (Function2): function done in parallel. c) Function1 [Function2]: equivalent function.
1996 Dec 11
7
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
6 6.1 SYSTEM CONTROL Memory organization 6.2
P90CL301BFH (C100)
Programmable chip-select
The maximum external address space of the controller is 16 Mbytes. It can be partitioned into five address spaces. These address spaces are designated as either User or Supervisor space and as either Program or Data space or as interrupt acknowledge. For slow memories the CPU can be programmed to insert a number of wait states. This is done via the eight Chip-select Control Registers CS0N to CS7N; further to be denoted as CSnN, where n = 0 to 7. The number of inserted wait states can vary from 0 to 6, or wait states are inserted until the DTACK is pulled LOW by the external address decoding circuitry. If DTACK is asserted continuously, the P90CL301BFH will run without wait states using bus cycles of three or four clock periods depending on the state of the FBC bit in the SYSCON register. 6.1.1 MEMORY MAP
In order to reduce the external components associated with memory interface, the P90CL301BFH provides 8 programmable chip-selects. A specific chip-select CSBT provides default reset values to support a bootstrap operation. Each chip-select can be programmed with: * A base address (A23 to A19) * A memory bank width of 512 kbytes, 1, 2, 4 or 8 Mbytes memory size * A number of wait states (0 to 6 states, or wait for DTACK) to adapt the bus cycle to the memory cycle time. Chip-selects can be synchronized with read, write, or both read and write, either Address strobe or Data strobe. They can also be programmed to address low byte, high byte or word. Each chip-select is controlled by a control register CSnN (n = 0 to 7). The control registers are described in Table 3 to 7. The RESET instruction does not affect the contents of the CSnN registers. Register CS7N corresponds to register CSBT (address FFFF 8A0EH). After reset CSBT is programmed with a block size of 8 Mbytes with: * A19 to A23 at logic 0 * M19 to M22 at logic 1 * 6 wait states * read only mode. The other chip-selects are held HIGH and will be activated after initialization of their control registers. When programmed in reduced access mode (read only, write only, low byte, high byte), the wait states are generated internally and if there is any access-violation when the bit WD in the SYSCON register is set to a logic 1 (time-out), the processor will execute a bus error after the time-out delay.
The memory address space is divided as shown in Table 2; short addressing space with A31 to A15 = 1. Table 2 Memory address space DESCRIPTION external 16 Mbytes memory not used off-chip 64 kbytes on 8051 bus not used
ADDRESS (HEX) 0000 0000 to 00FF FFFF 0100 0000 to 8000 FFFF 8001 0000 to 8001 FFFF 8002 0000 to FFFF 7FFF
FFFF 8000 to FFFF 8AFF internal registers FFFF 8B00 to FFFF 8FFF not used FFFF 9000 to FFFF 91FF internal 512 bytes RAM FFFF 9200 to FFFF BFFF not used FFFF C000 to FFFF C0FF internal 256 bytes Test-ROM FFFF C100 to FFFF FFFF not used
1996 Dec 11
8
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
6.2.1 Table 3 15 M22 Table 4 BIT 15 to 12 11 to 10 9 to 8 7 to 3 2 to 0 CHIP SELECT CONTROL REGISTERS (CS0N TO CS7N)
P90CL301BFH (C100)
Chip Select Control Registers CS0N to CS7N (address FFFF 8A00H to FFFF 8A0CH) 14 M21 13 M20 12 M19 11 RW1 10 RW0 9 MD1 8 MD0 7 A23 6 A22 5 A21 4 A20 3 A19 2 WS2 1 WS1 0 WS0
Description of CS0N to CS7N bits SYMBOL M22 to M19 DESCRIPTION Address mask for block size selection; see Table 5.
RW1 to RW0 Read/Write bus control (R/W); see Table 6. MD1 to MD0 MODE selection; see Table 7. A23 to A19 Decoded base address; this should be a multiple of the block size (other codes are reserved for test or reset state); after reset: A23 to A19 = 11111 except for CSBT.
WS2 to WS0 Wait states 0 to 6 (see Table 8); 7 wait states for DTACK to be pulled LOW by the external address decoding circuitry. The default value after reset is `110B' for CSBT and `111B' for the other chip-selects. Table 8 WS2 0 0 0 0 1 1 1 Note 1. The default value after a CPU reset. Wait states selection WS1 0 0 1 1 0 0 1 WS0 0 1 0 1 0 1 0 WAIT STATES 0 1 2 3 4 5 6(1)
Table 5 M22 0 0 0 0 1
Address mask for block size selection M21 0 0 0 1 1 M20 0 0 1 1 1 M19 0 1 1 1 1 BLOCK SIZE 512 kbytes 1 Mbyte 2 Mbytes 4 Mbytes 8 Mbytes; default value after a CPU reset
Table 6 RW1 0 0 1 1
Read/Write bits (R/W) RW0 0 1 0 1 FUNCTION Read only with length of AS Write only with length of DS Write only with length of AS Read/write with length of AS; default value after a CPU reset
Table 7 MD1 0 0 1 1
Mode selection MD0 0 1 0 1 FUNCTION Alternate function Low byte access only High byte access only Word access; default value after a CPU reset
1996 Dec 11
9
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
Table 9 Number of clock periods per bus cycle Number of clock periods per bus cycle, dependent on the programmed length of FBC (Fast Bus Cycle bit in the SYSCON register) and CSn (chip-select). LENGTH OF CSn = LENGTH OF AS WAIT STATES 0 1 2 3 4 5 6 6.3 3 4 5 6 7 8 9 FBC = 1 READ WRITE 4 4 5 6 7 8 9 FBC = 0 R/W 4 4 5 6 7 8 9 LENGTH OF CSn = LENGTH OF DS FBC = 1 READ 3 4 5 6 7 8 9 WRITE 4 5 6 7 8 9 10 FBC = 0 READ 4 4 5 6 7 8 9 WRITE 4 5 6 7 8 9 10
Dynamic bus port sizing
The memory bus size can be selected to be 16 or 8-bit wide depending on the ports width of external memories and peripherals. It is possible via the register BSREG to define for each chip-select the bus width to 16-bit or 8-bit used for the transfer of data to or from external memory. The 7-bit register BSREG defines the bus size associated with each chip-select function (except for CSBT). The bus size of the chip-select boot CSBT (CS7N) is hardware defined by the pin BSIZE.The state of the pin BSIZE is latched at the end of the reset sequence. When an address generated by the CPU is identified by a chip-select block as belonging to it's address segment, the 6.3.1 BUS SIZE REGISTER (BSREG)
corresponding bit of the register BSREG is used to define the sequence of bus transfer in 16 or 8-bit mode. Several chip-selects with different bus sizes should not address the same memory segment. For each case the number of bus cycles necessary to transfer a byte, word or long word is a function of the bus size. For example, a word read on a 8-bit bus will take 2 bus cycles and the high byte is read first. The 8-bit port uses the pins D7 to D0. See Table 11 and 12 and also Section 6.2 for more detailed information on the programmable chip-selects and the dynamic bus sizing.
Table 10 Bus Size Register (address FFFF A811H) 7 - 6 BS6 5 BS5 4 BS4 3 BS3 2 BS2 1 BS1 0 BS0
Table 11 Description of BSREG bits BIT 7 6 to 0 SYMBOL - BS6 to BS0 Reserved. Bus size for the data transfer with respect to the corresponding chip-select (CS6 to CS0). If BSn = 0, then the bus size is in 16-bit mode; the default value after a CPU reset. If BSn = 1, then the bus size is in 8-bit mode. Where n = 0 to 6. DESCRIPTION
1996 Dec 11
10
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
Table 12 Bus size depending on BSIZE, CSBTX and BSn (n = 0 to 6) BUS SIZE OF CS0 TO CS6(1) PIN BSIZE 0 0 1 1 Notes 1. Depending on bit BSn in register BSREG. BIT CSBTX BSn = 0 0 1 0 1 16 bit 16 bit note 2 16 bit BSn = 1 8 bit 8 bit 8 bit 8 bit
P90CL301BFH (C100)
BUS SIZE OF CSBTX AT BOOT 16 16 8 8 AFTER BOOT 16 8 8 16 PORT PL AVAILABLE (P0 TO P7) no yes yes no
2. The default value after reset of bits BSn in register BSREG is logic 0 which corresponds to 16-bit mode for CS0 to CS6. In this case, it is recommended to set BSn to logic 1 in the boot routine. Afterwards if CSBTX is set to logic 1, BSn can be reset to logic 0 by software for further transfers in 16-bit mode. 6.4 System Control Register (SYSCON)
The P90CL301BFH uses a System Control Register (SYSCON) for adjusting system parameters. Table 13 System Control Register (address FFFF 8000H) 15 14 13 12 11 10 9 8 7(1) 6(1) 5 4 3 2 1(2) IDL 0 DOFF
WDSC BPE CSBTX STBY PCLK3 PCLK2 PDE GF PCLK1 PCLK0 IM WD FBC PD Notes
1. The default values after a CPU reset: PCLK1 = 1 and PCLK0 = 1; all other SYSCON bits are a logic 0. 2. All bits are reset by the RESET instruction, except the IDL bit which is only reset by a CPU reset.
1996 Dec 11
11
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
Table 14 Description of SYSCON bits BIT 15 SYMBOL WDSC DESCRIPTION
P90CL301BFH (C100)
Bus error Watchdog short cycle. WDSC = 0 for normal mode; the bus error Watchdog counts 2048 periods before activating the bus error sequence. WDSC = 1 for Bus error Watchdog short cycle; the Watchdog counts 16 periods before activating the bus error sequence. Bus pull-up enable. If BPE = 0, the Address and Data bus internal pull-ups are switched off. If BPE = 1, the Address and Data bus internal pull-ups are switched on. Invert bus size for chip select boot and mode of port P0 to P7. CSBTX = 0 for normal mode; bus size is defined by the pin BSIZE. If CSBTX = 1, the chip select boot is defined by the inverted value of the pin BSIZE. The mode change should be executed from the internal RAM or from a memory activated by any other chip select than CSBT. For further details see also Section 6.3. CPU Standby mode. STBY = 0, for normal mode. STBY = 1, for Standby mode; only the CPU clock is switched off, the peripheral clocks are still running (see Fig.4).
14 13
BPE CSBTX
12 11, 7 and 6 10
STBY
PCLK3, PCLK1 Prescaler for primary peripheral clock (FCLK) and the UART clock in mode 0. and PCLK0 The CPU clock = CLK; FCLK = 1divisor x CLK. See Table 15 for the divisor values. PCLK2 Prescaler for secondary peripheral clock FCLK2 (derived from the primary peripheral clock FCLK), used for the ADC; the maximum value of the FCLK2 clock is dependent on the supply voltage VDD; see Section 19. If PCLK2 = 0, then FCLK is divided by 2; if PCLK2 = 1, then FCLK is divided by 4. If PDE = 0, then bits A22 to A19 are in normal operation; If PDE =1, then bits A22 to A19 are used as 8051 peripheral chip-select PCS3 to PCS0. General purpose flag bit; reset to a logic 0 after CPU reset. For IM = 0, level 7 is loaded into the Status Register during interrupt processing to prevent the CPU from being interrupted by another interrupt source. For IM = 1, the current interrupt level is loaded into the Status Register allowing nested interrupts. For WD = 0, the time-out for bus error detection is switched off. If the time-out is not used, the Watchdog Timer can be used to stop a non-acknowledged bus transfer. For WD = 1, the time-out for bus error detection is activated. If no DTACK has been sent by the addressed device after 128 x 16 internal clock cycles the on-chip bus error signal is activated. FBC = 0, normal bus cycle; FBC = 1, fast bus cycle. An external read bus cycle can take a minimum of 3 clock periods; the minimum write cycle is still 4 clock periods; in order to get this access time DTACK should be asserted on time. PD = 0, for normal mode; PD = 1, for Power-down mode (see Section 6.8). IDL = 0, for normal mode; IDL = 1, for Idle mode (see Section 6.8). DOFF = 0, for normal mode. DOFF = 1, for delay counter off; if set at wake-up from Power-down the delay counter waiting period is skipped.
9 8 5
PDE GF IM
4
WD
3
FBC
2 1 0
PD IDL DOFF
1996 Dec 11
12
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
Table 15 Selection of prescaler divisor values PCLK3 0 0 0 0 1 1 1 6.5 PCLK1 0 0 1 1 0 1 1 Reset operation PCLK0 0 1 0 1 1 0 1 DIVISOR (D) 2 3 4 5 (default value after a CPU reset) 6 8 10
P90CL301BFH (C100)
DIVISOR FOR UART IN MODE 0 6 6 6 6 12 12 12
The reset circuitry of the P90CL301BFH is connected to the pins RESET, HALT, RESETIN and to the internal Watchdog Timer. A Schmitt trigger is used at the input pin for noise rejection. After Power-on a CPU reset is accomplished by holding the RESET pin and the HALT pin LOW for at least 50 oscillator clocks after the oscillator has stabilized. For further information on the clock generation, see Section 6.6. The CPU responds by reading the reset vectors; the long word at address 000000H is loaded into the Supervisor stack and the long word data at address 000004H is loaded into the program counter PC. The interrupt level is set to 7 in the Status Register and execution starts at the PC location. By pulling the RESET pin LOW and keeping HALT HIGH, only the peripherals are reset. When VDD is turned on and its rise time does not exceed 10 ms, an automatic reset can be performed by connecting the RESETIN pin to VDD via an external capacitor. The external capacitor is charged via an internal pull-down resistor.
The RESET pin can also be pulled LOW internally by a pull-down transistor activated by an overflow of the Watchdog Timer. When the CPU executes a RESET instruction, the RESET pin is pulled LOW. When the CPU is internally halted (at double bus fault), the HALT pin is pulled LOW and only a CPU reset can restart the processor. The internal signal RESET_AS (Reset Asynchronous) resets the core and all registers. When an internal Watchdog Timer overflow occurs, an internal CPU reset is generated which resets all registers except the SYSCON, PCON, PRL and PRH registers and pulls the RESET pin LOW during 12 clock cycles.
1996 Dec 11
13
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
handbook, full pagewidth
instruction RESET
RESET
peripheral reset
LATCH CLK Watchdog reset
RESET_AS
CPU-reset LATCH CLK Watchdog reset double bus fault
HALT
CPU HALT
VDD external reset capacitor
Rstin
RESETIN
MBG330
Fig.3 Reset circuitry.
1996 Dec 11
14
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
6.6 Clock generation
P90CL301BFH (C100)
The prescaler is controlled by the System Control Register (SYSCON). The internal clock is divided by a factor 2, 3, 4, 5, 6, 8 or 10 (function of bits PCLK0, PCLK1 and PCLK3; see Table 15). For the ADC a secondary peripheral clock FCLK2 is derived from the peripheral clock by dividing it either by 4 or 2 (function of the bit PCLK2; see Table 14).
An external clock can be used with the P90CL301BFH. The duty cycle of the external clock should be 50/50 5% over the full temperature and voltage range. For peripherals like Watchdog Timer, I2C-bus, PWM, Timer and baud rate generator, a programmable prescaler generates a peripheral clock FCLK.
handbook, full pagewidth
XTAL1 SYSCON (IDL)
Idle mode
1/512 CPU
CLK SYSCON (PCLK3) 1 1/2
mode 0 clock 1/3 1/4 FCLK 1/5 BCON 1 1/4 UART1
SYSCON (PCLK0, 1)
1/2
SYSCON (PCLK2)
SCON 1/4 FCLK2 1/2
BRG
UART0
PRESCALER
TIMER 0/TIMER 1
ADC
S1CON
I2C-BUS INTERFACE
PWM0/PWM1
WATCHDOG
MGD781
Fig.4 P90CL301BFH internal clock generation.
1996 Dec 11
15
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
6.7 Interrupt controller
P90CL301BFH (C100)
Table 16 Priority order SIGNAL NMIN INT6 INT5 INT4 INT3 INT2 INT1 INT0 I2C-bus ADC UART1 receiver UART1 transmitter UART0 receiver UART0 transmitter Timer 1 Timer 0 6.7.2 EXTERNAL LATCHED INTERRUPTS lowest PRIORITY ORDER highest
An interrupt controller handles all internal and external interrupts. It delivers the interrupt with the highest priority level to the CPU. The following interrupt requests are generated by the on-chip peripherals: * I2C-bus * UARTs: received data / transmitted data * Timers: two flags for the timers T0 and T1 * ADC: analog-to-digital conversion completed. The external interrupt requests are generated with the pins NMIN and the seven external interrupts INT0 to INT6. 6.7.1 INTERRUPT ARBITRATION
The interrupt priority levels are programmable with a value between 0 and 7. Level 7 has the highest priority, level 0 disables the corresponding interrupt source. In case of interrupt requests of equal priority level at the same time a hardware priority mechanism gives priority order as shown in Table 16. The execution of interrupt routines can be interrupted by another interrupt request of a higher priority level. In 68070 mode (SYSCON bit IM = 1) when an interrupt is serviced by the CPU, the corresponding level is loaded into the Status Register. This prevents the current interrupt from getting interrupted by any other interrupt request on the same or a lower priority level. If IM is reset, priority level 7 will always be loaded into the Status Register and so the current interrupt cannot be interrupted by an interrupt request of a level less than 7. Each on-chip peripheral unit including the eight interrupt lines generate only auto-vectored interrupts. No acknowledge is necessary. For external interrupts the vectors 25 to 31 are used, for on-chip peripheral circuits a second table of 7 vectors are used (57 to 63); see Section 7.3.2.
NMIN and INT0 to INT6 are 8 external interrupt inputs. These pins are connected to the interrupt function only when the corresponding bit in the SPCON control register is set (see Section 8.2; Table 29). Seven interrupt inputs INT0 to INT6 are edge sensitive on HIGH-to-LOW transition and their priority levels are programmable. The interrupt NMIN is non-maskable (except if it is programmed as a port) and is also edge sensitive on HIGH-to-LOW transition. The priority level of NMIN is fixed to 7. The external interrupts are controlled by the registers LIR0 to LIR3; see Tables 17 and 18.
6.7.2.1
Latched Interrupt Registers (LIR0 to LIR3)
Table 17 Latched Interrupt Registers ADDRESS FFF 8101H FFF 8103H FFF 8105H FFF 8107H REGISTER LIR0 LIR1 LIR2 LIR3 7 PIR1 PIR3 PIR5 PIR7 6 IPL1.2 IPL3.2 IPL5.2 1 5 IPL1.1 IPL3.1 IPL5.1 1 4 IPL1.0 IPL3.0 IPL5.0 1 3 PIR0 PIR2 PIR4 PIR6 2 IPL0.2 IPL2.2 IPL4.2 IPL6.2 1 IPL0.1 IPL2.1 IPL4.1 IPL6.1 0 IPL0.0 IPL2.0 IPL4.0 IPL6.0
1996 Dec 11
16
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
Table 18 Description of LIR0 to LIR3 bits BIT 7 and 3 SYMBOL PIRn
P90CL301BFH (C100)
DESCRIPTION Pending interrupt request. n = 0 to 7; INT7 corresponds to the interrupt NMIN; PIRn = 1, pending interrupt request for pin INTn. PIRn = 0 (default value after a CPU reset), no pending interrupt. When a valid interrupt request has been detected this bit is set. It is automatically reset by the interrupt acknowledge cycle from the CPU. It can be reset by software by writing a logic 0, however writing a logic 1 has no effect on the flag. To reset only one flag, a logic 0 should be written to the bit address and a logic 1 to the other interrupt requests. The use of BCLR instruction should be avoided (PIR7 is cleared when the pin NMIN is set HIGH) Interrupt priority level of pins INT0 to INT6 (fixed to `111B' for NMIN in LIR3); m = 0 to 6.
6 to 4 2 to 0
IPLm.2 to IPLm.0
6.7.2.2
Pending Interrupt Flag Register (PIFR)
An additional register PIFR contains copies of the PIR flags. The PIF flags are set at the same time as the PIR flags when an interrupt is activated, but these flags are not reset automatically during the interrupt acknowledge cycle. They can only be cleared by software and keep a trace of the interrupt event. The detection of an external interrupt is indicated by the corresponding PIF-bit being set to a logic 1. Table 19 Pending Interrupt Flag Register (address FFFF 810F) 7 PIF7 6.7.3 6 PIF6 5 PIF5 4 PIF4 3 PIF3 2 PIF2 1 PIF1 0 PIF0
NOTE ON SIMULTANEOUS INTERRUPTS
If an internal interrupt is immediately followed by an external interrupt (i.e. both interrupts occurring within 12 clock cycles) and both these interrupts have the same interrupt level, then the CPU might hang up during the acknowledge cycle of the internal interrupt. In the interrupt controller a flag WIN is set for each interrupt as soon as the interrupt is activated and will be reset when an interrupt of higher priority occurs or during the acknowledge cycle. The WIN flag is used to determine which PIR flag should be reset. A conflict occurs if within the interval starting at the CPU sampling of the first internal interrupt and ending at the acknowledge cycle, a second external interrupt resets the WIN flag of the first interrupt (external interrupts have higher priority than internal).
When the CPU acknowledges the first internal interrupt the auto-vector acknowledge signal cannot be asserted as its WIN flag was reset, and the CPU hangs up. This situation can be solved by using the bus time-out counter controlled by the System Control Register (SYSCON) with the bits WD and WDSC set. In the case of hang-up an internal bus error condition will be asserted after 16 clocks and the CPU will execute the exception SPURIOUS INTERRUPT at vector 60H. In the exception service routine the interrupt flags PIR should be polled to detect which interrupts caused the conflict, the corresponding PIR flags should be cleared by software and a call to the interrupt routines executed.
1996 Dec 11
17
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
6.8 Power reduction modes 6.8.2
P90CL301BFH (C100)
STANDBY MODE
The P90CL301BFH supports three power reduction modes. A Power-down mode where the clock is frozen, a Standby mode where only the CPU is stopped, and an Idle mode where the external clock is divided by 512 (see Fig.4). 6.8.1 POWER-DOWN MODE
When the STBY bit in the SYSCON register is set, the CPU clock is stopped and the status of the processor is frozen, however, the clocks of all other on-chip peripherals are still running at the nominal frequency; these peripherals are: * Timers * External and internal interrupts * UARTs and baud rate generator * I2C-bus interface * Watchdog Timer * PWMs * ADC. The CPU exits this mode when an internal or external interrupt is activated, and proceeds with the normal program execution. For minimum power consumption internal pull-ups on address and data buses can be switched on by setting the control bit BPE in the SYSCON register. The pull-ups should be switched off in normal mode if not needed. 6.8.3 IDLE MODE
The Power-down operation freezes the oscillator. It can only be activated by setting the PD bit in the SYSCON register and thereafter execute the STOP instruction. The instruction flow to enter the Power-down mode is: BSET #PD, SYSCON STOP #$2700. In this state all the register contents are preserved. The CPU remains in this state until an internal reset occurs or a LOW level is present on any of the external interrupt pins INT0 to INT6 or NMIN. If the wake-up is done via an external interrupt, the processor will first execute an external interrupt of level 7. If the IPL level in the LIR register is set to 7, a second interrupt of level 7 will be executed. It is preferable to set the IPL to 0. In Power-down mode VDD may be reduced to minimize power consumption. However, the supply voltage must not be reduced until Power-down mode is active, and must be restored before a external reset or an interrupt is activated. In case of an external reset, the pin should be held active until the external oscillator has restarted and stabilized. In case of an external interrupt wake-up, any INTn or NMIN pin should go LOW and the corresponding bit ESn (n = 0 to 7) in register SPCON should be set. If the DOFF bit in the SYSCON is not set, an internal delay counter ensures that the internal clock is not active before 1536 clock cycles. After that time the oscillator is stable and normal exception processing can be executed. The PD bit is cleared automatically during the wake-up. In order to have a fast start-up the DOFF bit should be set, switching off the delay counter and enabling the immediate clocking and restart of the controller. For minimum power consumption during Power-down mode, the address and data pins should be pulled HIGH externally or bit BPE in register SYSCON should be set (i.e. internal pull-ups enabled).
In the Idle mode the crystal or external clock is divided by a factor 512. The current is reduced drastically but the controller continues to operate. This mode is entered by setting the bit IDL in the SYSCON register. The next instruction will be executed at a slower speed. To return to normal mode the IDL bit should be reset. It should be noted that all peripheral functions are also slowed down, and some cannot be used normally, for example UART, I2C-bus, ADC and PWM. The Power-down mode can also be entered from the Idle mode. After a wake-up the controller restarts in Idle mode.
1996 Dec 11
18
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
7 7.1 CPU FUNCTIONAL DESCRIPTION General 7.2
P90CL301BFH (C100)
Programming model and data organization
The CPU of the P90CL301BFH is software compatible with the Motorola MC68000, hence programs written for the MC68000 will run on the P90CL301BFH without modifications. However, for certain applications the following differences between processors should be noted: * Differences exist in the address/bus error exception processing since the P90CL301BFH can provide full error recovery. * The timing is different for the P90CL301BFH due to a new internal architecture and technology. The instruction execution timing is different for the same reasons.
The programming model is identical to that of the MC68000 (see Fig.5), with seventeen 32-bit registers, a 32-bit Program Counter and a 16-bit Status Register. The eight data registers (D0 to D7) are used for byte, word and long-word operations. The Address Registers (A0 to A6) and the System Stack Pointer A7 can be used as software stack pointers and base address registers. In addition, these registers can be used for word and long-word address operations. All seventeen registers can be used as index registers. The P90CL301BFH supports 8, 16 and 32-bit integers as well as BCD data and 32-bit addresses. Each data type is arranged in the memory as shown in Fig.6.
Table 20 Format of the Status Register and description of the bits; r = reserved 15 T Trace mode 14 - r 13 S Supervisor 12 - r 11 - 10 12 9 11 8 10 7 - 6 - r 5 - 4 X 3 N 2 Z Zero 1 V 0 C
Interrupt mask
Extend Negative
Overflow Carry
1996 Dec 11
19
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
31
ndbook, full pagewidth
16 15
8
7
0 DO D1 D2 D3 Eight Data D4 Registers D5 D6 D7
31
16 15
0 A0 A1 A2 Seven A3 Address Registers A4 A5 A6
USER STACK POINTER SUPERVISOR STACK POINTER 31 0
A7
Two Stack Pointers
Program Counter 15 SYSTEM BYTE 8 7 USER BYTE 0 Status Register
MCD504
Fig.5 Programming model.
1996 Dec 11
20
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
bit
7
6
5
4
3
2
1
0
(a) Bit data (1 Byte = 8 bits).
bit 15
14 13
12 11 10 BYTE 0 BYTE 2
9
8 LSB
7
6
5
4
3
2
1
0
MSB
BYTE 1 BYTE 3
(b) Integer data (1 Byte = 8 bits).
bit 15 14 13 12 11 10 MSB
9
8
7
6
5
4
3
2
1
0 LSB
WORD 0 WORD 1 WORD 2 (c) Word data (16 bits).
bit 15 14 13 12 11 10 MSB LONG WORD 0
9
8
7
6
5
4
3
2
1
0
HIGH ORDER LOW ORDER HIGH ORDER LOW ORDER HIGH ORDER LONG WORD 2 LOW ORDER LSB
LONG WORD 1
(d) Long-word data (32 bits).
bit 15 14 13 12 11 10 MSB
9
8
7
6
5
4
3
2
1
0
ADDRESS 0
HIGH ORDER LOW ORDER LSB
ADDRESS 1
HIGH ORDER LOW ORDER HIGH ORDER
ADDRESS 2
LOW ORDER
(e) Addresses (1 address =32 bits).
bit 15 14 13 12 11 10 MSB BCD 0 BCD 4 BCD 1 BCD 5
9
8 LSB
7
6
5
4
3
2 BCD 3 BCD 7
1
0
BCD 2 BCD 6
(f) BCD data (2 BCD digits = 1 Byte).
MCD505
Fig.6 Memory data organization.
1996 Dec 11
21
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
7.3 Processing states and exception processing 7.3.1
P90CL301BFH (C100)
REFERENCE CLASSIFICATION
The P90CL301BFH operates with a maximum internal clock frequency of 27 MHz down to static operation. Each clock cycle is divided into 2 states. A non-access machine cycle has 3 clock cycles or 6 states (S0 to S5). A minimum bus cycle normally consists of 3 clock cycles (6 states). When DTACK is not asserted, indicating that data transfer has not yet been terminated, wait states (WS) are inserted in multiples of 2. The CPU is always in one of the four processing states: * Normal * Exception * Halt * Stopped. The Normal processing state is associated with instruction execution; the memory references fetch instructions or load/save results. A special case of the Normal state is the Stopped state which is entered by the processor when a STOP instruction is executed. In this state the CPU does not make any further memory references. The Exception state is associated with interrupts, trap instruction, tracing and other exceptional conditions. The exception may be generated internally by an instruction or by any unusual condition arising during the execution of an instruction. Externally, exception processing can be forced by an interrupt or by reset. The halted processing state is an indication of a catastrophic hardware failure. For example, if during exception processing of a bus error another bus error occurs, the CPU assumes that the system is unusable and halts. Only an external reset can restart a halted processor. Note that a CPU in the stopped state is not in the halted state or vice versa. The Supervisor can work in the User or Supervisor state determined by the state of bit S in the Status Register. Accesses to the on-chip peripherals are achieved in the Supervisor state. All exception processing is performed in the Supervisor state once the current contents of the Status Register has been saved. Then the exception vector number is determined and copies of the Status Register, the program counter and the format/vector number are saved on the Supervisor stack using the Supervisor Stack Pointer (SSP). Finally the contents of the exception vector location is fetched and loaded into the Program Counter (PC).
When the processor makes a reference, it classifies the kind of reference being made, using the encoding of the three function code internal lines. This allows external translation of addresses, control of access, and differentiation of special processor states, such as interrupt acknowledge. Table 21 shows the classification of references. Table 21 Reference classification FUNCTION CODE REFERENCE CLASS FC2 0 0 0 0 1 1 1 1 7.3.2 FC1 0 0 1 1 0 0 1 1 FC0 0 1 0 1 0 1 0 1 unassigned User Data User Program unassigned unassigned Supervisor Data Supervisor Program interrupt acknowledge
EXCEPTION VECTORS
Exception vectors are memory locations from where the CPU fetches the address of a routine that will handle that exception. All exception vectors are 2 words long, except for the reset vector which consists of 4 words, containing the PC and the SSP. All exception vectors are in the Supervisor Data space. A vector number is an 8-bit number which, multiplied by 4, gives the address of an exception vector. Vector numbers are generated internally. The memory map for the exception vectors is shown in the Table 22.
1996 Dec 11
22
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
Table 22 Exception vector assignment VECTOR NO. 0 - 2 3 4 5 6 7 8 9 10 11 12(1) 13(1) 14 15 16 to 23(1) 24 25 26 27 28 29 30 31 32 to 47 48 to 56(1) 57 58 59 60 61 62 63 64 to 255 Note 1. Vectors 12, 13, 16 to 23 and 48 to 56 are reserved for future enhancements. DECIMAL 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 to 95 96 100 104 108 112 116 120 124 128 to 191 192 to 227 228 232 236 240 244 248 252 256 to 1023 HEX 000 004 008 00C 010 014 018 01C 020 024 028 02C 030 034 038 03C 040 to 05C 060 064 068 06C 070 074 078 07C 080 to 0BF 0C0 to 0E3 0E4 0E8 0EC 0F0 0F4 0F8 0FC 100 to 3FF reset: initial SSP reset: initial PC bus error address error illegal instruction zero divide CHK instruction TRAPV instruction privilege violation trace line 1010 emulator line 1111 emulator
P90CL301BFH (C100)
ASSIGNMENT
unassigned, reserved unassigned, reserved format error uninitialized interrupt vector unassigned, reserved spurious interrupt level 1 external interrupt auto-vector level 2 external interrupt auto-vector level 3 external interrupt auto-vector level 4 external interrupt auto-vector level 5 external interrupt auto-vector level 6 external interrupt auto-vector level 7 external interrupt auto-vector TRAP instruction vectors reserved level 1 on-chip interrupt auto-vector level 2 on-chip interrupt auto-vector level 3 on-chip interrupt auto-vector level 4 on-chip interrupt auto-vector level 5 on-chip interrupt auto-vector level 6 on-chip interrupt auto-vector level 7 on-chip interrupt auto-vector reserved
1996 Dec 11
23
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
7.3.3 INSTRUCTION TRAPS
P90CL301BFH (C100)
The trace facility uses the T-bit in the Supervisor part of the Status Register. If the T-bit is cleared, tracing is disabled and instructions are executed normally. If the T-bit is set at the beginning of the execution of an instruction, a trace exception will be generated once the instruction has been executed. If the instruction is not executed, either because of an interrupt, or because the instruction is illegal or privileged, the trace exception does also not occur if the instruction is aborted by a reset, bus error, or address error exception. If the instruction is executed, and an interrupt is pending, the trace exception is processed before the interrupt. If the execution of an instruction forces an exception, the forced exception is processed before the trace exception. As an extreme illustration of the above rules, consider the arrival of an interrupt during the execution of a TRAP instruction, while tracing is enabled. First the trap exception is processed, followed by the trace exception, and finally the interrupt handling routine. 7.5 Stack format
Traps are exceptions caused by instructions arising from CPU recognition of abnormal conditions during instruction execution or from instructions whose normal behaviour is to cause traps. Some instructions are used specifically to generate traps. The TRAP instruction always forces an exception and is useful for implementing system calls for User Programs. The TRAPV and CHK instructions force an exception if the User Program detects a run-time error, possibly an arithmetic overflow or a subscript out of bounds. The signed divide (DIVS) and unsigned divide (DIVU) instructions will force an exception if a divide-by-zero operation is attempted. 7.3.4 ILLEGAL AND UNIMPLEMENTED INSTRUCTIONS
Illegal instruction is the term used to refer to any word that is not the first word of a legal instruction. During execution, if such an instruction is fetched an illegal exception occurs. Words with bits 15 to 12 equal to `1010' or `1111' are defined as unimplemented instructions and separate exception vectors are allocated to these patterns for efficient emulation. This facility means the operating system can detect program errors, or can emulate unimplemented instructions in software. 7.3.5 PRIVILEGE VIOLATIONS
The stack format for exception processing is similar to the MC68010 although the instruction stored is not the same, due to the different architecture. To handle this format the P90CL301BFH differs from the MC68000 in that: * The stack format is changed. * The minimum number of words put into or restored from stack is 4 (MC68010 compatible, not 3 as with the MC68000). * The RTE instruction decides (with the aid of the 4 format bits) whether or not more information has to be restored as follows: - The P90CL301BFH long format is used for bus errors and address error exceptions. - All other exceptions use the short format. * If another format code, other than those listed above, is detected during the restored action, a FORMAT ERROR occurs. If the user wants to finish the instruction in which the bus or address error occurred, the P90CL301BFH format must be used on RTE. If no changes to the stack are required during exception processing, the stack format is transparent to the user.
To provide system security, various instructions are privileged and any attempt to execute one of the privileged instruction while the CPU is in the User state provokes an exception. The privileged instructions are: * STOP * RESET * RTE * MOVE to SR * AND (word) immediate to SR * EOR (word) immediate to SR * OR (word) immediate to SR * MOVE to USP. 7.4 Tracing
The CPU includes a facility to trace instructions one by one to assist in program development. In the trace state, after each instruction is executed, an exception is forced so that the debugging program can monitor execution of the program under test.
1996 Dec 11
24
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
dbook, full pagewidth
SP
SR PCH PCL FORMAT (4 bits) BASE VECTOR ADDRESS SSW MM INTERNAL INFORMATION INTERNAL INFORMATION Short Stack Format
Long Stack Format
TPDH TPDL TPFH TPFL DBINH DBINL IR IRC INTERNAL INFORMATION
MBG426
Fig.7 Stack format; see Table 23.
Table 23 Description of the stack format SYMBOL SR PCH/PCL FORMAT BASE VECTOR ADDRESS SSW MM TPDH/TPDL TPFH/TPFL DBINH/DBINL IR IRC 1996 Dec 11 Status Register. Program Counter High/Low Word. Indicating either a short stack (only the first four words), or the long for bus and address error exceptions. The base vector address of the exception in the vector table; e.g. 8 for a bus error and 12 for an address error. Special Status Word. Current Move Multiple Mask. In the event of faulty write cycle, the data can be found here. The address used during the faulty bus cycle. Data that has been read prior to the faulty bus cycle can in some cases be found here. Holds the present instruction executed. Holds either the present instruction executed or the prefetched instruction. 25 DESCRIPTION
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
7.6 CPU interrupt processing
P90CL301BFH (C100)
As all P90CL301BFH interrupts are auto-vectored, the processor internally generates a vector number corresponding to the interrupt level number. The processor starts normal exception processing by saving the format word, program counter and Status Register on the Supervisor stack. The value of the vector in the format word is an internally generated vector number multiplied by 4 (format is all zeros). The program counter value is the address of the instruction that would have been executed if the interrupt had not been present. Then the interrupt vector contents are fetched and loaded into the program counter. The interrupt handling routine starts with normal instruction execution. 7.7 Bus arbitration
The general interrupt handling mechanism is described in Section 6.7. An interrupt controller handles all interrupts, resolves the priority problem and passes the highest level interrupt to the CPU. The CPU interrupt handling follows the same basic rules as in the MC68000. However, some remarks must be made: * Interrupts with a priority level equal to or lower than the current priority level will not be accepted. * During the acknowledge cycle of an interrupt, the IPL bits of the Status Register are set to the priority of the acknowledged interrupt or to 7. An exception occurs when bit IM = 0 (SYSCON bit 5). In this case level 7 is loaded into the Status Register (see Section 6.4; Table 14). If the priority level of the pending interrupt is greater than the current processor priority then: * The exception processing sequence is started * A copy of the Status Register is saved * The privilege level is set to Supervisor state * Tracing is suppressed * The priority level of the processor is set to that of the interrupt being acknowledged or to 7 depending on the IM flag in the System Control Register. The processor then gets the vector number from the interrupting device, classifies it as an interrupt acknowledge and displays the interrupt level number being acknowledged on the internal address bus.
If the HALT pin is held LOW with RESET HIGH the CPU will stop after completion of the current bus cycle. As long as HALT is LOW, all control signals are inactive and all 3-state lines are placed in the high-impedance state. If the HALT pin is held LOW during the transfer of a word in 8-bit mode, the CPU will continue the transfer of the two bytes before it halts.
1996 Dec 11
26
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
8 PORTS
P90CL301BFH (C100)
Each port pin consists of a latch, an output driver with pull-ups and an input buffer. To use the port as input the port latch should be written with a logic 1. This means only a weak pull-up is on and can be overwritten by an external source logic 0. When outputting a logic 1, a strong pull-up is turned on only for 1 clock period, and then only the weak pull-up maintains the HIGH level. In read mode, two different internal addresses correspond to the port latch or the port pin.The port values are read via register PPL and PPH. After reset all ports are initialized as input, and the pins are connected to the port latch with exception for the pin NMIN/SP7 which is connected to the interrupt block.
For general purpose input/output operations the following ports can be used: * 16-bit bidirectional port lines P15 to P0 composed of two 8-bit ports PL (P7 to P0) and PH (P15 to P8) * 8-bit port lines SP7 to SP0. All port pins are multiplexed with other functions, but each one can be individually switched to the port function by setting the corresponding bit in the Port P Control Register (PCON) for `port Pn' and Port SP Control Register (SPCON) for `port SPn'. The port P7 to P0 is multiplexed with the data bus D15 to D8 and is selected by the pin BSIZE. 8.1 Port P Control Register (PCON)
The port Pn is controlled via the Port P Control Register (PCON). The register PCON is only reset by an external reset, and not by the RESET instruction. The port latches are accessed through the registers PRL and PRH. Table 24 Port P Control Register (address FFFF 8503H) 7 E15 6 E14 5 E13 4 E12 3 E11 2 E10 1 E9 0 E8
Table 25 Description of PCON bits BIT 7 to 0 SYMBOL E15 to E8 DESCRIPTION If En = 0, then `port Pn' is enabled; if En = 1, then the alternate function is enabled; n = 8 to 15. The default value after reset is logic 0.
8.1.1
PORT P LATCHES
Table 26 Port P Latch least significant byte (PRL; address FFFF 8505H) 7 P7 6 P6 5 P5 4 P4 3 P3 2 P2 1 P1 0 P0
Table 27 Port Latches High most significant byte (PRH; address FFFF 8509H) 7 P15 6 P14 5 P13 4 P12 3 P11 2 P10 1 P9 0 P8
1996 Dec 11
27
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
8.2 Port SP Control Register (SPCON)
P90CL301BFH (C100)
The special ports SPn (SP0 to SP7) consist of 8 I/O lines and are controlled via the two registers SPCON and SPR. The registers SPCON and SPR are reset by a peripheral reset. The port latch is accessed through the register SPR. 8.2.1 PORT SP CONTROL REGISTER (SPCON)
Table 28 Port SP Control Register (address FFFF 8109H) 7 ES7 6 ES6 5 ES5 4 ES4 3 ES3 2 ES2 1 ES1 0 ES0
Table 29 Description of SPCON bits BIT 7 to 0 SYMBOL ES7 to ES0 DESCRIPTION If ESn = 0, then `port SPn' is enabled; if ESn = 1, then the alternate function is enabled; n = 0 to 7. The default value after reset is logic 0, except for ES7 which is set at reset.
8.2.2
PORT SP LATCH (SPR)
Table 30 Port SP latch (FFFF 810BH) 7 SP7 8.2.3 6 SP6 5 SP5 4 SP4 3 SP3 2 SP2 1 SP1 0 SP0
ALTERNATIVE FUNCTIONS FOR PORTS P AND SP
Table 31 Alternative functions for P0 to P15 and SP0 to SP7 pins Functions within brackets are parallel functions. PORT PIN P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 D8 D9 D10 D11 D12 D13 D14 D15 PWM0 (CP0) PWM1 (CP1) SCL SDA ALTERNATE FUNCTION P12 P13 P14 P15 SP0 SP1 SP2 SP3 SP4 SP5 SP6 SP7 PORT PIN ALTERNATE FUNCTION ADC0 ADC1 ADC2 ADC3 RX1/INT0 TX1/INT1 (CLK0) RX0/INT2 (CP2) TX0/INT3 (CP3) INT4 (CP4) INT5 (CP5) INT6 (CLK1) NMIN
1996 Dec 11
28
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
handbook, full pagewidth
VDD
from port latch Q
DELAY p p p
I/O pin n
data input
MGD784
a. WP2 + WP4 port.
handbook, full pagewidth
VDD
from port latch Q
DELAY p p p
I/O pin n
data input
enable
ADC BLOCK CIA virtual ground
p
n
MGD787
b. AN + WP2 (P15 to P12) port.
Fig.8 Port schematics (continued in Fig.9).
1996 Dec 11
29
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
handbook, full pagewidth
external pull-up
pin n
data input
MGD783
a. Open-drain port.
handbook, halfpage
VDD
handbook, halfpage
VDD
p RVref pin n power down pin n
MGD786
data input
MGD785
b. 3-state port.
c. AREF input.
Fig.9 Port schematics (continued from Fig.8).
9
8051 PERIPHERAL BUS
The P90CL301BFH can also directly access the peripheral circuits which are compatible with the 8048/8051 bus. When the CPU accesses locations located in the 64 kbytes peripheral space, an Address/Data multiplexed access is generated using the AD0 to AD7 lines, the non-multiplexed A8 to A15 lines and the 8051 control bus (ALE, RD, WR). In order to use these three signals the alternate mode of the CS5 to CS3 should be set. A 8051 bus access is performed by addressing a byte in the 8001 0000H to 8001 FFFFH range.
To reduce the number of interface circuits, the address lines A22 to A19 can be used as peripheral chip-select outputs PCS0 to PCS3. This is done by setting the PDE bit (SYSCON) to a logic 1; * PCS0 selects memory range 0 kbytes to 16 kbytes * PCS1 selects memory range 16 kbytes to 32 kbytes * PCS2 selects memory range 32 kbytes to 48 kbytes * PCS3 selects memory range 48 kbytes to 64 kbytes. The timing of the peripheral bus is fixed and compatible with the 8051 peripheral circuits.
1996 Dec 11
30
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
10 ON-CHIP PERIPHERAL FUNCTIONS The P90CL301BFH integrates a number of peripheral functions connected to the internal bus: * Timers (T0 and T1) * Watchdog * 2 UART interfaces with one UART queue controller using the internal RAM as data buffers. * I2C-bus interface * PWM (Pulse Width Modulation) * ADC (Analog-to-Digital Converter). These functions are accessible as memory locations on a byte or word basis. The access is auto-acknowledged by on-chip logic. The on-chip peripheral functions can generate auto-vectored interrupts to the CPU using the second vector table (vectors 57 to 63). 10.1.1 TIMER INTERRUPT REGISTER (PICR0) 10.1
P90CL301BFH (C100)
Peripheral interrupt control
The timers T0 and T1, I2C-bus, UART and ADC use a common set of Peripheral Interrupt Control Registers (PICRn; n = 0 to 3). These registers are accessible from the CPU and contain the Interrupt Priority Level flags IPL2 to IPL0 as well as the Pending Interrupt flags PIR. PIR is set when a valid interrupt request has been detected. It is automatically reset by the interrupt acknowledge cycle from the CPU. The PIR flag can be reset by software. The Interrupt Priority Level code `111B' represents the interrupt with the highest priority. The code `000B' inhibits the interrupt.
On timer overflow or on channel capture/match the pending interrupt request flag PIRTn is set. If the interrupt priority level is different from zero, the timer activates an interrupt to the CPU. Table 32 Timer Interrupt Register (address FFFF 8701H) 7 PIRT1 6 IPLT1.2 5 IPLT1.1 4 IPLT1.0 3 PIRT0 2 IPLT0.2 1 IPLT0.1 0 IPLT0.0
Table 33 Description of PICR0 bits BIT 7 6 to 4 3 2 to 0 SYMBOL PIRT1 IPLT1.2 to IPLT1.0 PIRT0 IPLT0.2 to IPLT0.0 DESCRIPTION pending interrupt for timer T1 interrupt priority level for timer T1 pending interrupt for timer T0 interrupt priority level for timer T0
1996 Dec 11
31
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
10.1.2 UART INTERRUPT REGISTERS
P90CL301BFH (C100)
Each UART can generate two interrupts in transmission and reception via the two registers PICR1 and PICR2. Table 34 UART Interrupt Registers PICR1 (address FFFF 8703H) 7 PIRR0 6 IPLR0.2 5 IPLR0.1 4 IPLR0.0 3 PIRT0 2 IPLT0.2 1 IPLT0.1 0 IPLT0.0
Table 35 Description of PICR1 bits BIT 7 6 to 4 3 2 to 0 SYMBOL PIRR0 IPLR0.2 to IPLR0.0 PIRT0 IPLT0.2 to IPLT0.0 DESCRIPTION pending interrupt for UART0 in reception interrupt priority level for UART0 in reception pending interrupt for UART0 in transmission interrupt priority level for UART0 in transmission
Table 36 UART Interrupt Registers PICR2 (address FFFF 8705H) 7 PIRR1 6 IPLR1.2 5 IPLR1.2 4 IPLR1.2 3 PIRT1 2 IPLT1.2 1 IPLT1.1 0 IPLT1.0
Table 37 Description of PICR2 bits BIT 7 6 to 4 3 2 to 0 10.1.3 SYMBOL PIRR1 IPLR1.2 to IPLR1.0 PIRT1 IPLT1.2 to IPLT1.0 DESCRIPTION pending interrupt for UART1 in reception interrupt priority level for UART1 in reception pending interrupt for UART1 in transmission interrupt priority level for UART1 in transmission
I2C-BUS AND ADC INTERRUPT REGISTER (PICR3)
The I2C-bus and the ADC respectively, can generate one interrupt. Table 38 I2C-bus and ADC Interrupt Register (address FFFF 8707H) 7 PIRI 6 IPLI2 5 IPLI1 4 IPLI0 3 PIRA 2 IPLA2 1 IPLA1 0 IPLA0
Table 39 Description of PICR3 bits BIT 7 6 to 4 3 2 to 0 SYMBOL PIRI IPLI2 to IPLI0 PIRA IPLA2 to IPLA0 pending interrupt for I2C-bus DESCRIPTION interrupt priority level for I2C-bus pending interrupt for ADC interrupt priority level for ADC
1996 Dec 11
32
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
11 TIMERS 11.1 Timer array
P90CL301BFH (C100)
The 16-bit counter register is incremented at each prescaler overflow. When the counter reaches FFFFH, the status flag TOV is set and on the next clock the counter reload value is loaded into the counter. By resetting the control bit RUN in the timer control register the timebase is stopped, and by setting this bit, the prescaler and counter are reloaded and incremented on the next external or internal clock. 11.3 Channel function
Two identical 16-bit timer blocks are provided: * Timer 0 (T0) * Timer 1 (T1). Each timer block consists of: * A timebase * Three capture/compare channels * A Control Register * A Status Register. 11.2 Timebase
Each channel consists of a register and an equality comparator. For each of the three channels two modes can be selected: * Compare mode: sets the status flag CFn in TnSR when there is a match between the counter register and the channel register value. * Capture mode: stores the counter register value into the channel register and sets the status flag CFn when a transition occurs at the corresponding input pin CPn. In both modes, each channel can generate a global interrupt request if the corresponding enable bit in the Control Register TnCR is set.
The timebase contains an 8-bit prescaler with a write only reload register, and a 16-bit counter register. This counter register can only be read by software. The prescaler is clocked either by the peripheral clock FCLK or by an external clock enabled by the flag C/TN in the timer control register TnCR (T0CT for timer T0 and T1CR for timer T1). On prescaler overflow the prescaler reload value is loaded into the prescaler, which starts incrementing. 11.4 Pin parallel functions for the timer
In order to use the multiplexed pins for the timer, the other functions using these pins as output pins should be forced HIGH via a weak pull-up, enabling an external source to drive them LOW. Table 40 Parallel functions PIN SETTING PARALLEL FUNCTION CLK0 CP2 CP3 CP4 CP5 CLK1 CP0 CP1
SP1/TX1/INT1 if SPCON.1 = 0, SPR.1 = 1; else UART1 should not be used SP2/RX0/INT2 if SPCON.2 = 0, SPR.2 = 1; else UART0 should not be used SP3/TX0/INT3 if SPCON.3 = 0, SPR.3 = 1; else UART0 should not be used SP4/INT4 SP5/INT5 SP6/INT6 P8/PWM0 P9/PWM1 if SPCON.4 = 0, SPR.4 = 1 if SPCON.5 = 0, SPR.5 = 1 if SPCON.6 = 0, SPR.6 = 1 if PCON.0 = 0, PWM0 should output a logic 1 (write 00H to register PWM0) if PCON.1 = 0, PWM1 should output a logic 1 (write 00H to register PWM1)
1996 Dec 11
33
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
handbook, full pagewidth
PIRT0 (PIRT1)
internal bus 4 4 TOV
TIMER STATUS REGISTER T0SR (T1SR)
16 4 CHANNEL REGISTER T0C2 (T1C5) 16 16 COMPARE UNIT C2F (C5F) EDGE DETECTION CP2 (CP5)
16 16 CHANNEL REGISTER T0C1 (T1C4) 16 16 COMPARE UNIT C1F (C4F) EDGE DETECTION CP1 (CP4)
16 16 CHANNEL REGISTER T0C0 (T1C3) 16 16 COMPARE UNIT C0F (C3F) EDGE DETECTION CP0 (CP3)
16
16
16 COUNTER REGISTER T0 (T1) PRESCALER 0 1 16 8 PRESCALER RELOAD REGISTER FCLK CLK0 (CLK1)
16
COUNTER RELOAD REGISTER T0RR (T1RR)
8 CP0 (CP3)
GATE 16 TIMER CONTROL REGISTER T0CR (T1CR)
C/TN
MBG332
Fig.10 Timer block diagram T0 (identical with timer block T1, corresponding names indicated within brackets).
1996 Dec 11
34
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
11.5 Timer Control Registers
P90CL301BFH (C100)
The Timer 0 (T0) is controlled via Timer 0 Control Registers (T0CRH and T0CRL), and Timer 1 (T1) via Timer 1 Control Registers (T1CRH and T1CRL); see Fig.10 and Tables 41 to 44. The default value after a CPU reset for all bits of T0CRH; T1CRH; T0CRL and T1CRL is a logic 0. Table 41 Timer Control Registers T0CRH and T1CRH ADDRESS FFFF 8300H FFFF 8310H REGISTER T0CRH T1CRH 15 ECM2 14 C2M2 13 C2M1 12 C2M0 11 ECM1 10 C1M2 9 C1M1 8 C1M0
Table 42 Timer Control Registers T0CRL and T1CRL ADDRESS FFFF 8301H FFFF 8311H REGISTER T0CRL T1CRL 7 ECM0 6 C0M2 5 C0M1 4 C0M0 3 ETOV 2 GATE 1 C/TN 0 RUN
Table 43 Description of T0CRH; T1CRH; T0CRL and T1CRL bits BIT SYMBOL DESCRIPTION ECMn = 0, the channel n interrupt is disabled; ECMn = 1, the channel n interrupt is enabled. 14 to 12 10 to 8 6 to 4 3 C2M2 to C2M0 Channel mode; see Table 44. C1M2 to C1M0 C0M2 to C0M0 ETOV Timer overflow interrupt enable; ETOV = 0, the timer overflow interrupt is disabled; ETOV = 1, the timer overflow interrupt is enabled. 2 GATE Gated external clock; GATE = 0, disable gate function; GATE = 1, the prescaler increments only if the CP0 pin is HIGH for each rising edge transition of CLK0 if C/TN = 1 or with FCLK if C/TN = 0. 1 C/TN Counter/timer mode; C/TN = 0, timer mode; the prescaler is incremented on the rising edge of the peripheral clock (FCLK); C/TN = 1, counter mode; the prescaler increments on the rising edge of CLK0 for Timer 0 (CLK1 for Timer 1). 0 RUN Timer run enable; RUN = 0, timer prescaler stopped and registers value held; RUN = 1, when set the prescaler and counter are loaded and the prescaler is then incremented.
15, 11 and 7 ECM2 to ECM0 Channel n interrupt enable (n = 0 to 2);
1996 Dec 11
35
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
Table 44 Description of channel mode; n = 0 to 5; X = don't care CnM2 0 0 0 0 1 11.6 CnM1 0 0 1 1 X CnM0 0 1 0 1 X channel n inhibited
P90CL301BFH (C100)
DESCRIPTION channel n capture on LOW-to-HIGH transition of pin CPn channel n capture on HIGH-to-LOW transition of pin CPn channel n capture on any transitions of pin CPn channel compare mode
Timer Status Registers
Four events can occur: a timer overflow or three channel matches/captures. These event flags are stored in the 4-bit Timer 0 Status Register (T0SR for T0) and Timer 1 Status Register (T1SR for T1). They can be cleared by software but cannot be set. By writing a logic 1 the flags stay unchanged. In order to clear a particular flag one has to write a logic 0 to the corresponding position and logic 1s to the others. One should avoid to use the instruction BCLR, which can reset accidentally several flags. 11.6.1 TIMER 0 STATUS REGISTER (T0SR)
Table 45 Timer 0 Status Register (address FFFF 830DH) 7 - 6 - 5 - 4 - 3 C2F 2 C1F 1 C0F 0 TOV
Table 46 Description of T0SR bits BIT 7 to 4 3 to 1 0 SYMBOL - C2F to C0F TOV Reserved. Channel n event flag (n = 2 to 0); CnF = 0, no event (default value after a CPU reset). CnF = 1, capture mode: a capture occurred. Timer Overflow Flag; TOV = 0, no overflow (default value after a CPU reset). TOV = 1, timer overflow occurred. DESCRIPTION
11.6.2
TIMER 1 STATUS REGISTER (T1SR)
Table 47 Timer 1 Status Register (address FFFF 831DH) 7 - 6 - 5 - 4 - 3 C5F 2 C4F 1 C3F 0 TOV
Table 48 Description of T1SR bits BIT 7 to 4 3 to 1 0 SYMBOL - C5F to C3F TOV Reserved. Channel n event flag (n = 5 to 3); CnF = 0, no event (default value after a CPU reset). CnF = 1, capture mode: a capture occurred. Timer Overflow Flag; TOV = 0, no overflow (default value after a CPU reset). TOV = 1, timer overflow occurred. DESCRIPTION
1996 Dec 11
36
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
11.7 Watchdog Timer
P90CL301BFH (C100)
For FCLK in MHz, the Watchdog period is: 8192 ( 256 - WDTIM ) x -------------- s FCLK The Watchdog Timer is controlled by the register WDCON. A value of A5H in WDCON clears both the prescaler and timer WDTIM. After reset, WDCON contains A5H. Every value other than A5H in WDCON enables the Watchdog Timer. Since the bit 0 of the WDCON input is tied to a logic 0 by hardware during write operations on WDCON, the reset value A5H can not be programmed again and can only be restored by a reset. Timer WDTIM can be written only if WDCON has previously been loaded with 5AH, otherwise WDTIM and the prescaler are not affected. A successful write operation to WDTIM also clears the prescaler and clears WDCON. Only the values A5H or 5AH are stored, all other values are stored with a dummy value 00H.
The P90CL301BFH contains a Watchdog Timer consisting of a 13-bit prescaler and an 8-bit timer WDTIM. The prescaler is incremented by the peripheral clock. The 8-bit timer is incremented every 8192 cycles of the peripheral clock FCLK. If the FCLK frequency is 2 MHz, the Watchdog Timer can operate in the range of 4.1 ms up to 1 s. The Watchdog Timer is disabled after reset. It can be enabled by writing any value to the WDCON register. The only way to disable a running Watchdog Timer is to reset the P90CL301BFH. When a timer overflow occurs the microcontroller will be reset (except registers SYSCON, PCON, PRL and PRH which will not be reset). To prevent an overflow of the Watchdog Timer, the User Program must reload the Watchdog register within a period shorter than the programmed timer interval. This timer interval is determined by the 8-bit timer value written to the register WDTIM.
handbook, full pagewidth
FCLK
PRESCALER 13-BIT
FCLK/8192
COUNTER REGISTER 8-BIT
overflow Internal reset
enable
WDCON REGISTER
WDTIM 8-BIT RELOAD REGISTER
INTERNAL BUS
MBG325
Fig.11 Watchdog Timer block diagram.
1996 Dec 11
37
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
12 SERIAL INTERFACES 12.1 UART interface
P90CL301BFH (C100)
Mode 2 11 bits are transmitted (through TXD) or received (through RXD): a start bit at logic 0, 8 data bits (LSB first) a programmable 9th data bit, and a stop bit at logic 1. On transmit the 9th bit is taken from the bit TB8 from the SCON register. On receive the 9th bit goes into RB8 of SCON, while the stop bit is ignored. The baud rate is equal to 1 x CLK. The UART clock should not exceed 6 4.5 Mbaud. Mode 3 Same as mode 2 except for the baud rate, which is given by the baud rate generator output BGCLK0 for the UART0 and BGCLK1 for the UART1. In all four modes, transmission is initiated by any instruction loading SBUF. In Mode 0, reception is initiated by the condition RI = 0 and REN = 1. In the remaining modes reception is initiated by the incoming start bit if REN = 1.
The UART can operate in 4 modes. The baud rate for receive and transmit can be generated internally or by the baud rate generator. The UART is full duplex, meaning it can receive and transmit simultaneously. The receive and transmit registers are both accessed as a unique register SBUF. Writing to SBUF loads the transmit register, and reading from SBUF accesses a physically separate receive register. 12.1.1 UART OPERATING MODES
The serial port can operate in one of the four modes: Mode 0 Serial data enters and exits through RXD. TXD pin delivers the synchronous shift clock. 8 bits are transmitted/received (LSB first). When the bit PCLK3 in the SYSCON register is reset, the baud rate is equal to 16 x CLK. When the bit PCLK3 in register SYSCON is set, the baud rate is equal to 1 x CLK. The UART baud rate should not 12 exceeds 4.5 Mbaud. Mode 1 10 bits are transmitted (through TXD) or received (through RXD): a start bit at logic 0, 8 data bits (LSB first) and a stop bit at logic 1. On receive the stop bit goes into RB8 in the register SCON. The baud rate is given by the baud rate generator output BGCLK0 for the UART0 and BGCLK1 for the UART1.
1996 Dec 11
38
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
12.1.2 UART CONTROL REGISTERS SCON0 AND SCON1
P90CL301BFH (C100)
The registers SCON0 and SCON1 control UART0 and UART1 modes respectively, and contain the interrupt flags. Table 49 UART Control Registers SCON0 and SCON1 ADDRESS FFFF 8603H FFFF 8607H REGISTER SCON0 SCON1 7 SM0 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI
Table 50 Description of register SCON0 and SCON1 bits BIT 7 to 6 5 SYMBOL SM0 to SM1 Mode bits; see Table 51. SM2 Multiprocessor; enable the multiprocessor communication feature in Modes 2 and 3. If SM2 is set the RI will not be activated if the received 9th data bit RB8 = 0. In Mode 1, if SM2 is set the RI will not be activated if a valid stop bit is not received. In Mode 0, SM2 should be a logic 0. Receive enable; enables serial reception; set and cleared by software. Transmit extra bit; 9th data bit that will be transmitted in Modes 2 and 3; set and cleared by software. Receive extra bit; in Modes 2 and 3, RB8 is the 9th bit received. In Mode 1, if SM2 = 0, RB8 is the stop bit which is received. Transmit interrupt; it is set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit in the other modes (except: see bit SM2). TI must be cleared by software (cannot be set by software). By writing a logic 1 the flags stay unchanged. In order to clear a particular flag one has to write a logic 0 to the corresponding position and a logic 1 to the others. One should avoid to use the instruction BCLR, which can reset accidentally several flags. Receive interrupt; set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit in the other modes (except: see SM2). RI must be cleared by software (cannot be set by software). By writing a logic 1 the flags stay unchanged. In order to clear a particular flag one has to write a logic 0 to the corresponding position and a logic 1 to the others. One should avoid to use the instruction BCLR, which can reset accidentally several flags. DESCRIPTION
4 3 2 1
REN TB8 RB8 TI
0
RI
Table 51 Mode defined by bits SM0 and SM1 SM0 0 0 1 1 SM1 0 1 0 1 MODE 0 1 2 3 shift register;
1 6
DESCRIPTION x CLK 8-bit UART; BGCLK0 and BGCLK1 9-bit UART; 116 x CLK 9-bit UART; BGCLK0 and BGCLK1
1996 Dec 11
39
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
12.2 Baud rate generator
P90CL301BFH (C100)
The timer is clocked by the peripheral clock. The baud rates for UART0 and UART1 in Mode 1 and 3 are determined by the timer overflow rate as follows (FCLK is in Hz): FCLK BGCLK0 = --------------------------------------------------------------( 16x ( 65536 - BREG ) ) FCLK BGCLK1 = ---------------------------------------------------------------------------------- BDIV 16 x ( 65536 - BREG ) x4
A dedicated baud rate generator is directly connected to the UART0. For the UART1 this clock can be divided by 1 or 4 as a function of the bit BDIV in the BCON control register. The baud rate generator consists of a 16-bit timer, two 8-bit registers BREGL (least significant byte) and BREGH (most significant byte) to store the 16-bit reload value, and a control register BCON. When an overflow occurs the timer is reloaded with the contents of the registers BREGH, BREGL. 12.2.1 UART BAUD RATE CONTROL REGISTER (BCON)
The default value after a CPU reset for all bits of BCON is a logic 0. Table 52 UART Baud Rate Control Register (address FFFF 860FH) 7 - 6 - 5 - 4 - 3 - 2 - 1 BST 0 BDIV
Table 53 Description of BCON bits BIT 7 to 2 1 0 12.3 SYMBOL - BST BDIV Reserved. BST = 0, stop timer; BST = 1, start timer increment after loading of timer register with the reload register value. BDIV = 0, UART1 baud rate not divided; BDIV = 1, UART1 baud rate divided by 4. The RAM can be accessed by the CPU any time. The queue controller accesses the RAM either in read mode for the transmission or in write mode for the reception. When the queue controller accesses the RAM, the CPU waits for the end of the access cycle (maximum 4 CLK clocks). The RAM space can be partitioned in one or several buffers for transmission or reception or for normal data storage. The maximum size of a buffer is limited to 256 bytes. In addition to these buffers the queue consists of a set of control and data registers: DESCRIPTION
UART queue
The UART queue performs the sending and receiving of a frame of bytes of variable length through the UART without the support of the CPU. Only the UART0 has a frame buffer located at the lower 256 bytes section of the internal RAM. A controller ensures the sequencing of the transfers between the RAM and the UART and generates interrupts to the CPU. This UART queue can be used for transmission and reception simultaneously or for only one of the two modes.
1996 Dec 11
40
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
data bus
handbook, full pagewidth
address bus
UQTS UQRS
UQRA UQTA
MUX
DECR zero
INCR MUX
RAM 256 BYTES data bus
UQRM UQRC UQTC MUX ten
=
UART QUEUE CONTROL TX SBUF0 RX SBUF0 TI RIF TIF SCON0 RI
MGD782
TX RX
Fig.12 UART queue block diagram.
Table 54 Function of UART queue registers NAME UQTC(1) UQTA(2) FUNCTION Transmission Control Register and Interrupt Flags. Transmit Buffer Address Register DESCRIPTION Reception control and status flags. Transmission control and status flags and interrupt flags. Start address of transmission buffer from 00H to FFH, corresponds to CPU address from FFFF 9000H to FFFF 90FFH. Size of the transmission buffer. Limited to 256 bytes. SIZE byte byte byte
UQRC(1) Reception Control Register
UQTS (2) Transmit Buffer Size Register UQRA(3)
byte byte
Reception Buffer Address Register Start address of reception buffer from 00H to FFH, corresponds to CPU address from FFFF 9000H to FFFF 90FFH. Size of the reception buffer. Limited to 256 bytes. The received characters are compared with the value contained in this register and an interrupt is generated when they are equal. Reception Match Register
UQRS(3) Reception Buffer Size Register UQRM
byte byte
Notes 1. UQRC and UQTC can be accessed together as a word or as two bytes. 2. For each byte transmitted the UQTA is incremented, the UQTS is decremented. 3. For each byte received the UQRA is incremented, the UQRS is decremented.The CPU can read this register on the fly, but in this case the accuracy is not guaranteed so it is recommended to halt the queue and read the values.
1996 Dec 11
41
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
12.3.1 RECEPTION CONTROL REGISTER (UQRC)
P90CL301BFH (C100)
In order to keep the bit unchanged when writing to the control register, it is recommended to write a logic 1 when it can only be reset, and to write a logic 0 when it can only be set. After peripheral reset all bits are set to a logic 0. Table 55 Reception Control Register (address FFFF 8B00H) BIT 7 ACTION OF REN CPU(1) QUEUE(2) Notes 1. CPU. R: the CPU can reset this bit. S: the CPU can set this bit. 2. QUEUE. R: the queue controller can reset this bit. S: the queue controller can set this bit. Table 56 Description of UQRC bits BIT 7 SYMBOL REN DESCRIPTION Receive queue enable. This bit enables the queue controller. It connects the reception data buffer SBUF0 to the queue controller. It should be set before activating the RSTF bit. When it is reset SBUF0 can be accessed directly by the CPU. REN = 0 means receive queue disable. Received byte can be read directly from SBUF0. REN = 1 means receive queue enable: The transfers from the SBUF0 to the RAM can be activated by setting the bit RSTF. Reception match enable. If it is set each received byte is compared with the content of the UART Queue Receive Match register (UQRM) and if their value match the receive interrupt flag RIF is set. RME = 0 means match function disabled. RME = 1 means match function enabled. Reception interrupt enable. When this bit is set, each time a byte is received the receive interrupt flag RIF is set. If it is not set, an interrupt is only generated at the end of the frame. RIE = 0 means no interrupt after the reception of each byte, only at the end of the frame. RIE = 1 means interrupt after the reception of each byte. Reception overflow enable. When this bit is set, the RSTF bit is not reset when the reception buffer size reached 0, setting the RIF flag, so the reception of further bytes is allowed. The bit ROF is not set because RSTF stays set. This bit can be set in conjunction of RAR to implement a circular buffer. ROE = 0 means no overflow enable. ROE = 1 means overflow enable. Reception overflow flag. This flag is set by the queue controller, when a character is received with the RSTF flag reset and REN set. This event can occur after the end of reception of a frame, and if the CPU had no time to unload the RAM and set RSTF. ROF = 0 means no overflow detection. ROF = 1 means overflow. S/R - RME S/R - RIE S/R - ROE S/R - ROF R S RAR S/R - RHLT S/R - RSTF S R BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
6
RME
5
RIE
4
ROE
3
ROF
1996 Dec 11
42
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
BIT 2
SYMBOL RAR
DESCRIPTION Reception address reset. If this flag is set, when the buffer size has been decremented to zero, the reception address is reset. This way a circular reception buffer can be located at address 0. RAR = 0 means no reset of reception address. RAR = 1 means reset of reception address. Reception halt. This bit is set by the CPU to interrupt the reception of the frame. The byte currently received by the UART will be stored in the buffer, but the next bytes will be lost until the CPU reset the bit RHLT. In order to stop all activity in the UART it is preferable to reset the bit REN reception enable of the register SCON0. RHLT = 0 means reception not halted. RHLT = 1 means reception halted. Reception start flag. This bit is set by the CPU to enable the reception of a frame through the UART and it is reset automatically by the queue controller at the end of reception. When RHLT is set this bit stays set. When REN is reset, this bit is reset. RSTF = 0 means reception not started or ended. RSTF = 1 means reception started and in progress.
1
RHLT
0
RSTF
12.3.2
TRANSMISSION CONTROL REGISTER AND INTERRUPT FLAGS (UQTC)
Table 57 Transmission Control Register and Interrupt Flags (address FFFF 8B01H) BIT 7 ACTION OF TIF CPU(1) QUEUE(2) Notes 1. CPU. R: the CPU can reset this bit. S: the CPU can set this bit. 2. QUEUE. R: the queue controller can reset this bit. S: the queue controller can set this bit. Table 58 Description of UQTC bits BIT 7 SYMBOL TIF DESCRIPTION Transmission interrupt flag. This flag is set either at the end of the transmission buffer or at the transmission of each byte if TIE is set. The TIF flag should be reset by the CPU in the exception routine in order to detect further interrupts as they are edge detected for LOW-to-HIGH transitions. Reception interrupt flag. This flag is set either at the end of the reception buffer or during a character match if RME is set or at the reception of each byte if RIE is set. The RIF flag should be reset by the CPU in the exception routine in order to detect further interrupts as they are edge detected for LOW-to-HIGH transitions. Reserved. Transmission interrupt waiting. TIWF = 0(1) means queue controller is not waiting for UART transmit interrupt.TIWF = 1 means queue controller is waiting for UART transmit interrupt. Transmission queue enable. TEN = 0(1) means transmission queue disable. Transmitted byte can be written directly into SBUF0. TEN = 1 means transmission queue enable; the transfers from the RAM to SBUF0 can be activated by setting the bit TSTF. R S RIF R S reserved - - TIWF - S/R TEN S/R - TIE S/R - THLT S/R - TSTF S R BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
6
RIF
5 4
- TIWF
3
TEN
1996 Dec 11
43
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
BIT 2
SYMBOL TIE
DESCRIPTION Transmission interrupt enable. If it is set, each time a byte is transmitted the transmit interrupt flag TIF is set. If it is not set, an interrupt is only generated at the end of the frame. TIE = 0(1) means no interrupt after the reception of each byte. TIE = 1 means interrupt after the reception of each byte. Halt transmission. This bit is set by the CPU to interrupt the transmission of the frame. The byte currently loaded in the UART will be transmitted entirely, but the next byte will wait until the CPU reset the bit HLTT. THLT = 0(1) means transmission not halted. THLT = 1 means transmission halted. Start transmission. This bit is set by the CPU to start the transmission of a frame through the UART and it is reset automatically by the queue controller at the end of transmission. TSTF = 0(1) means transmission not started or ended. TSTF = 1 means transmission started and in progress.
1
THLT
0
TSTF
Note 1. State after peripheral reset. 12.3.3 UART QUEUE REGISTERS
Table 59 UART Queue Registers REGISTER UQTA UQTS UQRA UQRS UQRM ADDRESS FFFF 8B03H FFFF 8B05H FFFF 8B07H FFFF 8B09H FFFF 8B0BH 7 A7 S7 A7 S7 M7 6 A6 S6 A6 S6 M6 5 A5 S5 A5 S5 M5 4 A4 S4 A4 S4 M4 3 A3 S3 A3 S3 M3 2 A2 S2 A2 S2 M2 1 A1 S1 A1 S1 M1 0 A0 S0 A0 S0 M0
1996 Dec 11
44
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
12.3.4 UART QUEUE OPERATION: TRANSMISSION
P90CL301BFH (C100)
12.3.5.1 Mode 0: Normal reception buffer.
The UART queue transmit operation is as follows: 1. The UART control register is initialized for a certain transmission mode (0, 1, 2 and 3) and the baud rate generator loaded for a defined baud rate. 2. The CPU loads the data to be transmitted (for example 80 characters) at successive addresses of the internal RAM starting at a certain base address (for example FFFF 9010H). Then it writes the buffer start address and the buffer size in the pointer registers, and initializes the control register. 3. The queue controller reads the byte at the address pointed by the address register and writes it to the transmit data buffer of the UART and the buffer size register is decremented, the address register is incremented pointing to the next byte in the buffer. The transmission starts. The controller waits for the end of transmission, then compares the buffer size value to zero, if they are not equal the same operation is repeated automatically. 4. If the buffer size is zero the transmit interrupt flag TIF is set issuing an interrupt to the CPU.The interrupt routine should reset TIF and can reload the buffer with other values. 5. Before checking the buffer size value, the halt bit THLT is tested and if it is set the controller enters a transmission wait state. Table 60 Transmission routine move.b #$50,UQTS ;buffer size move.b #$10,UQTA bset bset 12.3.5 STF,UQTC; ;buffer start address ;Start transmission. TEN,UQTC; ;Enable transmission queue
We want to receive 80 characters, store then in a buffer starting at the address FFFF 9020H and generate an interrupt. The CPU is able to down-load the 80 characters, before the reception of any further character. After reception of the first character the queue controller reads the data reception register SBUF0 and transfers it's contents into the buffer at the address of the UQRA register, at the same time the buffer size register UQRS is decremented, the address register UQRA is incremented to point to the next byte. If the buffer size is not equal to zero the same operation is repeated automatically for the next byte to be transmitted. If the buffer size is zero the receive interrupt flag RIF is set issuing an interrupt to the CPU. The interrupt routine should reset RIF and can read the content of the buffer and re-initialize the control registers. Table 61 Reception routine move.b #$50, UQRS move. bset bset #$20, UQRA REN, UQRC RSTF, UQRC ;set buffer size ;set buffer start address ;Enable queue controller ;Start reception.
Table 62 Interrupt routine move.b move.b move.l L1 move.l dbne #$BE,UQTC #$28,d0 #$FFFF9020,a0 #$00008000,a1 d0,L1 ;reset RIF bit ;buffer size in words ;buffer start address ;external memory start address ;loop
UART QUEUE OPERATION: RECEPTION
The UART queue reception operation is as follows: The UART control register is initialized for a certain reception mode (Mode 0, 1, 2 and 3) and the baud rate generator loaded for a defined baud rate. The CPU writes the buffer start address and the buffer size in the data registers, and the control register. Several modes can be used:
1996 Dec 11
45
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
12.3.5.2 Mode 1: Special termination character match. 12.3.5.4
P90CL301BFH (C100)
Mode 3: Circular buffer with interrupt.
Suppose that we want to generate an interrupt after the reception of a Carriage Return character, we load in the reception match register the value 0DH, to guarantee that the buffer does not overflow if the buffer size is limited to 80 characters. The buffer is located in RAM at the address FFFF 9050H. The same operations as described before are performed but in addition each received characters compared with the character Carriage Return and if they match the receive interrupt flag RIF is set, RSTF is reset and the reception queue is stopped. Table 63 Mode 1 routine move.b #$50,UQRS move.b #$50,UQRA move.b #$0d,UQRM bset bset bset Note 1. All these control bits can be set at the same time. REN,UQRC RME,UQRC RSTF,UQRC ; buffer size ; buffer start address ; set match character ; enable queue ; reception match enable ; start reception (note 1)
If we want to implement a circular buffer which generates an interrupt each time the size register is equal to 0, the UQRA address register is reset and points to the beginning of the RAM. Table 65 Mode 3 routine move.b #$50,UQRS move.b #$00,UQRA bset bset bset Note 1. All these control bits can be set at the same time. UART QUEUE OPERATION: RECEPTION HALT REN,UQRC RAR,UQRC RSTF,UQRC ; buffer size ; buffer start address ; enable queue ; reception reset address ; start reception (note 1)
12.3.6
Before to check the buffer size value, the halt bit HLTR0 is tested and if it is set the controller enters a reception wait state. 12.3.7 UART QUEUE OPERATION: EMULATION
12.3.5.3
Mode 2: Linear buffer with continuous reception.
When the pin PHALT (on the emulation package) is asserted LOW, the queue is halted the same way as when THLT and RHLT are set. The queue operation is continued when the pin PHALT is released HIGH.
If we want to continue to receive characters in the buffer after the end of the buffer and the setting of RIF: In this case RSTF is not reset at the end of the buffer, but the CPU will receive an interrupt (RIF = 1) when the size register UQRS equals zero. Table 64 Mode 2 routine move.b #$50,UQRS move.b #$50,UQRA bset bset bset Note 1. All these control bits can be set at the same time. REN,UQRC ROE,UQRC RSTF,UQRC ; buffer size ; buffer start address ; enable queue ; reception overflow enable ; start reception (note 1)
1996 Dec 11
46
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
12.4 I2C-bus interface
P90CL301BFH (C100)
These functions are controlled by the SCON register. SSTA is the Status Register whose contents may be used as a vector to various service routines. SDAT is the data shift register and SADR the slave address register. Slave address recognition is performed by hardware. For more details on the I2C-bus functions, see user manual "The I2C-bus and how to use it (including specifications)"; order number 9398 393 40011.
The serial port supports the twin line I2C-bus. The I2C-bus consists of a data line SDA and a clock line SCL. These lines also function as I/O port lines P11 and P10 respectively (always open drain). The system is unique because data transport, clock generation, address recognition and bus control arbitration are all controlled by hardware. The I2C-bus serial I/O has complete autonomy in byte handling and operates in four modes: * Master transmitter mode * Master receiver mode * Slave transmitter mode * Slave receiver mode. 12.5 Serial Control Register (SCON)
Table 66 Serial Control Register (address FFFF 8207H) 7 CR2 6 ENS 5 STA 4 STO 3 SI 2 AA 1 CR1 0 CR0
Table 67 Serial Control Register SCON bits BIT 7, 1 and 0 6 5 SYMBOL DESCRIPTION
CR2 to CR0 These three bits determine the serial clock frequency when SIO is in a master mode function of the peripheral clock FCLK (see Tables 68 and 69). ENS STA Enable serial I/O. If ENS = 0, the serial interface I/O is disabled and reset; if ENS = 1, the serial interface is enabled. Start flag. When this bit is set in slave mode, the hardware checks the I2C-bus and generates a START condition if the bus is free or after the bus becomes free. If the device operates in master mode it will generate a repeated START condition. Stop flag. If this bit is set in the master mode a STOP condition is generated. A STOP condition detected on the I2C-bus clears this bit. The STOP bit may also be set in slave mode in order to recover from an error condition. In this case no STOP condition is generated to the I2C-bus, but the hardware releases the SDA and SCL lines and switches to the not selected slave receiver mode. The STOP flag is cleared by the hardware. Serial Interrupt flag. This flag is set, and an interrupt is generated, after any of the following events occur: * A START condition is generated in master mode. * The own slave address has been received during AA = 1. * The general call address has been received while bit SADR.0 = 1 and AA = 1. * A data byte has been received or transmitted in master mode. * A data byte has been received or transmitted as selected slave. * A STOP or START condition is received as selected slave receiver or transmitter. While the SI flag is set, SCL remains LOW and the serial transfer is suspended. SI must be reset by software.
4
STO
3
SI
1996 Dec 11
47
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
BIT 2
SYMBOL AA
DESCRIPTION Assert Acknowledge When this bit is set, an acknowledge is returned after any one of the following conditions: * Slave address is received. * The general call address is received (bit SADR.0 = 1). * A data byte is received, while the device is programmed to be a master receiver. * A data byte is received, while the device is a selected slave receiver. When bit AA is reset, no acknowledgement is returned. Consequently, no interrupt is requested when the own slave address or general call address is received.
Table 68 CLK/SCL divide factor Values greater than 100 kbits are outside the specified frequency range. CLK/SCL DIVIDE FACTOR CR2 0 0 0 0 1 1 1 CR1 0 0 1 1 0 0 1 CR0 0 1 0 1 0 1 0 D = 2(1) 128 112 96 80 480 60 30 D=3 192 168 144 120 720 90 45 D=4 256 224 192 160 960 120 60 D=5 320 280 240 200 1200 150 75 D=6 384 336 288 240 1440 180 90 D=8 512 448 384 320 1920 240 120 D=10 640 560 480 400 2400 300 150
Table 69 I2C-bus serial clock rates Values greater than 100 kbits are outside the specified frequency range. BIT FREQUENCY (kHz) AT CLK = 26 MHz CR2 0 0 0 0 1 1 1 CR1 0 0 1 1 0 0 1 CR0 0 1 0 1 0 1 0 D = 2(1) - - - - 54 - - D=3 - - - - 36 - - D=4 101 - - - 27 - - D=5 81 93 - - 22 - - D=6 68 77 90 - 18 - - D=8 51 58 68 81 13 - - D = 10 41 46 54 65 10 87 -
Note to Tables 68 and 69 1. D = divisor = CLKFCLK; see Table 15.
1996 Dec 11
48
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
12.5.1 I2C-BUS STATUS REGISTER (SSTA)
P90CL301BFH (C100)
SSTA is an 8-bit read only Special Function Register. The contents of SSTA may be used as a vector to a service routine. This optimizes response time of the software and consequently that of the I2C-bus. Tables 73 to 77 show the list of the status codes defined by the contents of register SSTA. Table 70 I2C-bus Status Register (address FFFF 8205H) 7 SC4 6 SC3 5 SC2 4 SC1 3 SC0 2 - 1 - 0 -
Table 71 Description of SSTA bits BIT 7 to 3 2 to 0 SYMBOL SC4 to SC0 - Reserved; held LOW. DESCRIPTION The bits SC4 to SC0 hold a status code.
Table 72 Used abbreviations in the mode descriptions; see Tables 73 to 77 SYMBOL SLA R W ACK ACKNOT DATA MST SLV TRX REC 7-bit slave address read bit write bit acknowledgement (acknowledge bit = 0) not acknowledge (acknowledge bit = 1) 8-bit (byte) to or from the I2C-bus master slave transmitter receiver DESCRIPTION
Table 73 Master transmitter (MST/TRX) mode SSTA VALUE 08H 10H 18H 20H 28H 30H 38H DESCRIPTION A START condition has been transmitted A repeated START condition has been transmitted SLA and W have been transmitted, ACK has been received SLA and W have been transmitted, ACKNOT received DATA of S1DAT has been transmitted, ACK received DATA of S1DAT has been transmitted, ACKNOT received Arbitration lost in SLA, R/W or DATA
1996 Dec 11
49
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
Table 74 Master receiver (MST/REC) mode SSTA VALUE 38H 40H 48H 50H 58H Arbitration lost while returning ACKNOT SLA and R have been transmitted, ACK received SLA and R have been transmitted, ACKNOT received DATA has been received, ACK returned DATA has been received, ACKNOT returned DESCRIPTION
P90CL301BFH (C100)
Table 75 Slave transmitter (SLV/TRX) mode S1STA VALUE A8H B0H B8H C0H C8H Own SLA and R received, ACK returned Arbitration lost in SLA, R/W as MST. Own SLA and R received, ACK returned DATA byte has been transmitted, ACK received DATA byte has been transmitted, ACK received Last DATA byte has been transmitted, ACKNOT received DESCRIPTION
Table 76 Slave receiver (SLV/REC) mode SSTA VALUE 60H 68H 70H 78H 80H 88H 90H 98H A0H DESCRIPTION Own SLA and W have been received, ACK returned Arbitration lost in SLA, R/W as MST. Own SLA and W have been received, ACK returned General call has been received, ACK returned Arbitration lost in SLA, R/W as MST. General call received, ACK returned Previously addressed with own SLA. DATA byte received, ACK returned Previously addressed with own SLA. DATA byte received, ACKNOT returned Previously addressed with general call. DATA byte received, ACK has been returned Previously addressed with general call. DATA byte received, ACKNOT has been returned A STOP condition or repeated START condition received while still addressed as SLV/REC or SLV/TRX
Table 77 Miscellaneous S1STA VALUE 00H DESCRIPTION Bus error during MST mode or selected SLV mode, due to an erroneous START or STOP condition
1996 Dec 11
50
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
12.5.2 I2C-BUS DATA SHIFT REGISTER (SDAT)
P90CL301BFH (C100)
Table 78 I2C-bus Data Shift Register (address FFFF 8201H) 7 DATA.7 6 DATA.6 5 DATA.5 4 DATA.4 3 DATA.3 2 DATA.2 1 DATA.1 0 DATA.0
Table 79 Description of SDAT bits BIT 7 to 0 SYMBOL DATA.7 to DATA.0 DESCRIPTION The serial data to be transmitted or data that has just been received. Bit 7 is transmitted or received first; i.e. data is shifted from right to left.
12.5.3
I2C-BUS ADDRESS REGISTER (SADR)
This 8-bit register may be loaded with the 7-bit address to which the controller will respond when programmed as a slave receiver/transmitter. Table 80 I2C-bus Address Register (address FFFF 8203H) 7 SADR.7 6 SADR.6 5 SADR.5 4 SADR.4 3 SADR.3 2 SADR.2 1 SADR.1 0 SADR.0
Table 81 Description of SADR bits BIT 7 to 1 0 SYMBOL SADR.7 to SADR.1 SADR.0 Slave address. SADR.0 = GC, is used to determine whether the general CALL address is recognized. If GC = 0, general CALL address is not recognized (default value after a CPU reset). If GC = 1, general CALL address is recognized. DESCRIPTION
1996 Dec 11
51
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
13 PULSE WIDTH MODULATION (PWM) OUTPUTS Two Pulse Width Modulation outputs are provided on the P90CL301. These channels output pulses of programmable length and interval. The repetition frequency is defined by an 8-bit prescaler PWMP, which generates the clock for the counter. The 8-bit counter counts modulo 255 (from 0 to 254 inclusive). The prescaler and counter are used for the two channel outputs. The value of the 8-bit counter is compared to the content of the registers PWM0 (resp. PWM1) for the channel output PWM0 (resp. PWM1). Provided the content of this register is greater than the counter value, the output of PWM0 (resp. PWM1) is set LOW. If the content of this register is equal to, or less than the counter value, the output will stay high. The pulse width ratio is therefore defined by the content of the register PWM0 (respectively PWM1). 13.1 Prescaler PWM Register (PWMP)
P90CL301BFH (C100)
The pulse width ratio is in the range of 0 to 255255 and may be programmed in increments of 1255. The repetition frequency: FCLK f PWM = -------------------------------------------------- Hz ; for FCLK in Hz. ( 1 + PWMP ) x 255 When using a peripheral clock of 6 MHz for example, the above formula gives a repetition frequency range of 23 kHz to 91 Hz. By loading the PWM0 (resp. PWM1) with either 00H or FFH, the PWM0 output can be retained at a constant HIGH or LOW level respectively. When loading FFH to the PWM0 (respectively PWM1) register, the 8-bit counter will never actually reach this value.
Table 82 Prescaler PWM Register (address FFFF 8801H) 7 PWMP.7 6 PWMP.6 5 PWMP.5 4 PWMP.4 3 PWMP.3 2 PWMP.2 1 PWMP.1 0 PWMP.0
Table 83 Description of PWMP bits BIT 7 to 0 13.2 SYMBOL PWMP.7 to PWMP.0 DESCRIPTION Prescaler division factor = (PWMP + 1).
PWM Data Registers (PWM0 and PWM1)
Table 84 PWM Data Registers PWM0 and PWM1 ADDRESS FFFF 8803H FFFF 8805H REGISTER PWM0 PWM1 7 PWM0.7 PWM1.7 6 PWM0.6 PWM1.6 5 PWM0.5 PWM1.5 4 PWM0.4 PWM1.4 3 PWM0.3 PWM1.3 2 PWM0.2 PWM1.2 1 PWM0.1 PWM1.1 0 PWM0.0 PWM1.0
Table 85 Description of PWM0 and PWM1 bits; n = 0 to 1 BIT 7 to 0 SYMBOL PWMn.7 to PWMn.0 DESCRIPTION ( PWMn ) Pulse width ratio. LOW/HIGH ratio of PWMn signals = ----------------------------------------255 - ( PWMn )
1996 Dec 11
52
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
ndbook, full pagewidth
PWM0 REGISTER
I N T E R N A L B U S
8-BIT COMPARATOR
OUTPUT BUFFER
PWM0
FCLK
PWMP 8-BIT PRESCALER
8-BIT COUNTER
8-BIT COMPARATOR
OUTPUT BUFFER
PWM1
PWM1 REGISTER
MBG326
Fig.13 PWM block diagram.
1996 Dec 11
53
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
14 ANALOG-TO-DIGITAL CONVERTER (ADC) The analog input circuitry consist of a 4 input analog multiplexer and an analog-to-digital converter (ADC) with 8-bit resolution. The analog reference voltage Vref(A) and the analog supplies VDDA, VSSA are connected via separate input pins. The conversion time takes 24 periods of the secondary peripheral clock FCLK2 (see Section 6.6). The maximum value of the FCLK2 clock is dependant on the supply voltage (see Section 20). As the ADC is based on a successive approximation algorithm using a resistor scale connected to Vref(A) and VSSA, a continuous current flows in this resistor. 14.1 ADC Control Register (ADCON)
P90CL301BFH (C100)
By resetting the EADC bit in the control register ADCON or by entering Power-down it is possible to switch off this current to reduce the static power consumption. The ADC is controlled using the ADCON control register. Input channels are selected by the analog multiplexer function of register bits ADCON.0 and ADCON.1. The completion of the 8-bit ADC conversion is flagged by ADCI in the ADCON register and the result is stored in the register ADCDAT (address FFFF 8809H). The result of a completed conversion remains unaffected provided ADCI is HIGH. While ADCS or ADCI are HIGH, a new ADC start will be blocked and consequently lost. An ADC conversion already in progress is aborted when Power-down mode is entered.
Table 86 ADC Control Register (address FFFF 8807H) 7 - 6 EADC 5 - 4 ADCI 3 ADCS 2 - 1 A1 0 A0
Table 87 Description of ADCON bits BIT 7, 5 and 2 6 4 SYMBOL - EADC ADCI Reserved; set to LOW. ADC enable. If EADC = 1, then ADC is enabled. If EADC = 0, then ADC is disabled; the resistor reference is switched off to save power even while the CPU is operating. ADC interrupt flag. This flag is set when an ADC conversion result is ready to be read. An interrupt is invoked if the level IPLA is different from `0'. The flag must be cleared by software (it cannot be set by software). The ADCI bit must be cleared before a new conversion is started. ADC start and status. Setting this bit starts a conversion. The logic ensures that this signal is HIGH while the conversion is in progress. On completion, ADCS is reset at the same time the interrupt flag ADCI is set. ADCS cannot be reset by software. Analog input select. This binary coded address selects one of the four analog inputs ADC0 to ADC3. It can only be changed when ADCI and ADCS are both LOW. A1 is the MSB; e.g. `11' selects analog input channel ADC3. DESCRIPTION
3
ADCS
1, 0
A1, A0
Table 88 Operation of ADCI and ADCS ADCI 0 0 1 1 ADCS 0 1 0 1 OPERATION ADC not busy, a conversion can be started. ADC busy, start of a new conversion is blocked. Conversion completed, start of a new conversion is blocked. Intermediate status for a maximum of one machine cycle before conversion is completed (ADCI = 1, ADCS = 0).
1996 Dec 11
54
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
handbook, full pagewidth
VDDA +
AD0 AD1 AD2 AD3 START END
8-BIT ANALOG-TO-DIGITAL CONVERTER (succesive approximation) - +
Vref(A)
ANALOG INPUT MULTIPLEXER
LOGIC
V
SSA
ADCON
0 A0
1 A1
-
3 ADCS
4 ADCI
-
6 EADC
-
0
1
2
3
4
5
6
7
ADCDAT
PD (SYSCON.2) INTERNAL BUS
MGD779
Fig.14 Functional diagram of the ADC.
1996 Dec 11
55
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
15 ON-BOARD TEST CONCEPT To improve the on-board debugging two functions are implemented, the ON-Circuit Emulation (ONCE) mode and the on-chip Test-ROM. 15.1 ONCE mode
P90CL301BFH (C100)
The internal access time is in this case 3 cycles long. It can only be accessed in supervisor mode. The purpose of the Test-ROM is to offer the user a simple software interface to load programs for testing its own application and to transmit back the test result. The program can be loaded from the host into either the on-chip RAM or the external memory. The Test-ROM mode is entered by pulling LOW the R/W / TROM pin during reset. Just after the RESET initialization, the user should send a character of 9 bits (one stop bit plus eight data bits) with all bits being zero, on the RX0 line. Using the timer, the character length is captured and then the baud rate is automatically calculated and the baud rate generator is initialized. The UART0 is then initialized in Mode 3 with SM2 multiprocessor bit set, REN and TB8 bit set (SCON = F8H). The hardware is now ready to handle the protocol using the following 4 commands (Code 00 to 11).
The ON-Circuit Emulation (ONCE) mode eases the testing of an application without having to remove the controller from the board. The ONCE mode is entered by pulling CSBT LOW during reset. In this mode the address bus, data bus and bus control signals are in 3-state mode, all other output or bidirectional pins are weakly pulled HIGH. In this mode an emulator probe can be hooked-up to the circuit. Normal operation is restored with a normal reset. 15.2 Test-ROM
A second on-board debugging function is introduced for the situation where no extra connector can be placed on the PCB. It consists of an internal Test-ROM of 256 bytes which is used as boot ROM after a special test mode is activated during reset. The CPU will execute the code placed in the Test-ROM and initialize the UART0 and its baud rate generator and wait for commands to be sent to UART0. Table 89 Command format 7 Code Table 90 Command description BIT 7, 6 5 to 0 SYMBOL Code NB byte - 1 6 5 4
3 NB byte - 1
2
1
0
DESCRIPTION Pointer commands; see Table 91. Indicates the length of the transfer; e.g. (NB byte - 1) = 0 means a 1 byte transfer, (NB byte - 1) = 63 means a 64 byte transfer.
1996 Dec 11
56
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
Table 91 Pointer commands CODE DESCRIPTION BIT 7 BIT 6 0 0
P90CL301BFH (C100)
The pointer (A0 register) is initialized with a value depending of the number of transferred bytes. The most significant byte should be transferred first. Protocol: To start a data transfer, the pointer should be initialized first. It is incremented by one at each byte transfer between the memory and the host. The following registers are reserved for the protocol and should not be used by the user: D0, D1, D2, D3, A0, A1 and A2.
0 1 1
1 0 1
Read command. Read 1 to 64 bytes (load to the host). The pointer is incremented at each transfer. Write command. Write 1 to 64 bytes (load from the host). The pointer is incremented at each transfer. Jump command. If the NB field is 0 then a jump to the pointer address (A0) is done to start code execution. If the NB field 0, the complete protocol initialization is restarted (same effect as reset and R/W / TROM = 0).
handbook, full pagewidth
RESET
HALT
R/W / TROM Write command/data
RX0
9 bits baud rate calculation
TX0
data
MBG333
Fig.15 Test-ROM: Timing data transfer.
16 ON-CHIP RAM The P90CL301BFH contains a 512 bytes RAM which can be used to store program code or data. As this memory does not need wait states, it can speed up some time consuming tasks like stack operation, table references, or small program loops, compared with slow external memory or when using the 8-bit data bus. For a read or write access, 3 CPU clocks are used. The memory content is kept even when the supply voltage is lowered down to 1.8 V after entering Power-down mode. The base address is FFFF 9000H. It can be accessed in long word, word or bytes.
1996 Dec 11
57
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
17 REGISTER MAPPING
P90CL301BFH (C100)
The internal register map of the P90CL301BFH is summarized in Table 92. Note that the internal registers can be accessed: * only in Supervisor mode for version P90CL301BFH-3/4 * both in Supervisor and User mode for version P90CL301BFH-5. Table 92 Register map ADDRESS (HEX) SYMBOL WIDTH(1) STATE AFTER RESET (HEX)(2) REGISTER ACCESS(3)
System register FFFF 8000 SYSCON W 00C0 System Control Register R/W
Interrupt registers FFFF 8101 FFFF 8103 FFFF 8105 FFFF 8107 FFFF 810F LIR0 LIR1 LIR2 LIR3 PIFR B B B B B 00 00 00 00 00 Latched Interrupt 0/1 Register Latched Interrupt 2/3 Register Latched Interrupt 4/5 Register Latched Interrupt 6/7 Register Pending Interrupt Flag Register R/W R/W R/W R/W R/C
I2C-bus registers FFFF 8201 FFFF 8203 FFFF 8205 FFFF 8207 SDAT SADR SSTA SCON B B B B 00 00 F8 00 I2C-bus Data Register I2C-bus Address Register I2C-bus I2C-bus Status Register Control Register R/W R/W R R/W
Timers registers FFFF 8300 FFFF 8301 FFFF 8302 FFFF 8304 FFFF 8306 FFFF 8308 FFFF 830A FFFF 830D FFFF 830F FFFF 8310 FFFF 8311 FFFF 8312 FFFF 8314 FFFF 8316 FFFF 8318 FFFF 831A FFFF 831D T0CRH T0CRL T0RR T0 T0C0 T0C1 T0C2 T0SR T0PR T1CRH T1CRL T1RR T1 T1C0 T1C1 T1C2 T1SR B/W B W W W W W B B B/W B W W W W W B 0000 00 0000 0000 XXXX XXXX XXXX X0 00 0000 00 0000 0000 XXXX XXXX XXXX X0 Timer 0 Control Register (High byte) Timer 0 Control Register (Low byte) Timer 0 Reload Register Timer 0 Register Timer 0 Channel 0 Register Timer 0 Channel 1 Register Timer 0 Channel 2 Register Timer 0 Status Register Timer 0 Prescaler Reload Register Timer 1 Control Register (High byte) Timer 1 Control Register (Low byte) Timer 1 Reload Register Timer 1 Register Timer 1 Channel 0 Register Timer 1 Channel 1 Register Timer 1 Channel 2 Register Timer 1 Status Register R/W R/W W R R/W R/W R/W R/C W R/W R/W W R R/W R/W R/W R/C
1996 Dec 11
58
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
ADDRESS (HEX) FFFF 831F FFFF 8401 FFFF 8403
SYMBOL T1PR WDTIM WDCON
WIDTH(1) B B B
STATE AFTER RESET (HEX)(2) 00 00 A5
REGISTER Timer 1 Prescaler Reload Register Watchdog Timer Register Watchdog Control Register (only A5H or 5AH)
ACCESS(3) W R/W S
Port registers FFFF 8503 FFFF 8505 FFFF 8507 FFFF 8509 FFFF 850B FFFF 8109 FFFF 810B FFFF 810D PCON PRL PPL PRH PPH SPCON SPR SPP B B B B B B B B 00 FF FF FF FF 80 FF FF Port Control Register P Port Latch (least significant byte) P Port Pin (least significant byte) P Port Latch (most significant byte) P Port Pin (most significant byte) SP Port Control Register SP Port Latch SP Port Pin R/W R/W R R/W R R/W R/W R
UART registers FFFF 8601 FFFF 8603 FFFF 8605 FFFF 8607 SBUF0 SCON0 SBUF1 SCON1 B B B B XX 00 XX 00 UART0 Transmit/Receive Register UART0 Control Register UART1 Transmit/Receive Register UART1 Control Register R/W R/W R/W R/W
Baud rate generator registers FFFF 860B FFFF 860D FFFF 860F BREGL BREGH BCON B B B 00 00 00 UART Baud Rate Register (least significant byte) UART Baud Rate Register (most significant byte) UART Baud Rate Control Register R/W R/W R/W
Peripheral interrupt registers FFFF 8701 FFFF 8703 FFFF 8705 FFFF 8707 PICR0 PICR1 PICR2 PICR3 B B B B 00 00 00 00 Timer Interrupt Register UART0 Interrupt Register UART1 Interrupt Register I2C and ADC Interrupt Register R/W R/W R/W R/W
Pulse Width Modulation registers FFFF 8801 FFFF 8803 FFFF 8805 PWMP PWM0 PWM1 B B B 00 00 00 PWM Prescaler Register PWM0 Data Register PWM1 Data Register W R/W R/W
ADC registers FFFF 8807 FFFF 8809 ADCON ADCDAT B B 00 FF ADC Control Register ADC Data Register R/W R
Chip-select registers FFFF 8A00 1996 Dec 11 CS0N W FFFF Chip-select 0 Control Register 59 R/W
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
ADDRESS (HEX) FFFF 8A02 FFFF 8A04 FFFF 8A06 FFFF 8A08 FFFF 8A0A FFFF 8A0E FFFF 8A11 FFFF 8B00 FFFF 8B01 FFFF 8B03 FFFF 8B05 FFFF 8B07 FFFF 8B09 FFFF 8B0B Notes
SYMBOL CS1N CS2N CS3N CS4N CS5N CSBT BSREG UQRC UQTC UQTA UQTS UQRA UQRS UQRM
WIDTH(1) W W W W W W W B B B B B B B B
STATE AFTER RESET (HEX)(2) FFFF FFFF FFFF FFFF FFFF FFFF F306 00 00 00 00 00 00 00 00
REGISTER Chip-select 1 Control Register Chip-select 2 Control Register Chip-select 3 Control Register Chip-select 4 Control Register Chip-select 5 Control Register Chip-select 6 Control Register Chip-select Boot Control Register Bus Size Register UART Queue Receive Control Register UART Queue Transmit Control Register UART Queue Transmit Address Register UART Queue Transmit Status Register UART Queue Receive Address Register UART Queue Receive Status Register UART Queue Receive Match Register
ACCESS(3) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/C R/W R/C R/W
FFFF 8A0C CS6N
UART queue registers
1. Width when specified is in byte (B) or word (W). 2. X = don't care. 3. Access when specified is in read (R) write (W) or clear (C) only. The Watchdog Control Register is special (S).
1996 Dec 11
60
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
18 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI II, IO Ptot Tstg Tamb Tj supply voltage input voltage on any pin with respect to ground (VSS) DC current into any input or output total power dissipation storage temperature range operating ambient temperature range operating junction temperature range PARAMETER
P90CL301BFH (C100)
MIN. -0.5 -0.5 - - -65 -40 -
MAX. +3.6 5 300 +150 +85 +125 V VDD + 0.5 V
UNIT
mA mW C C C
19 DC CHARACTERISTICS VDD = 2.7 to 3.6 V; VSS = 0 V; Tamb = -40 to +85 C; all voltages with respect to VSS unless otherwise specified. SYMBOL Supply VDD IDD IDD(ID) IDD(STB) IDD(PD) Inputs VIL VIL VIH IIL ITL ITSI Outputs IOH4 IOH2 IOL8 IOL4 IOL2 CIN HIGH level output current; TS4 and OD4; note 4 VDD = 3 V; VOH = VDD - 0.4 V 4 13 7 24 15 8 - - - - - - 10 mA mA mA mA mA pF LOW level input voltage LOW level input voltage; D15 to D8, XTAL1, HALT, RESET, RESETIN HIGH level input voltage LOW level input current input current HIGH-to-LOW transition 3-state input current VDD = 3 V; VIN = 0.4 V VDD = 3 V; VIN = 0.5VDD VSS VSS - - 0.3VDD V 0.1VDD V VDD 50 500 10 V A A A supply voltage supply current operating; note 1 supply current Idle mode; note 2a supply current Standby mode; note 2b supply current Power-down mode; note 3 VDD = 3 V; CLK = 13.8 MHz VDD = 3 V; CLK = 27 MHz VDD = 3 V; CLK = 13.8 MHz VDD = 3 V; CLK = 27 MHz VDD = 3 V; CLK = 13.8 MHz VDD = 3 V; CLK = 27 MHz VDD = 3 V 2.7 - - - - - - - - 16 32 400 800 9 18 2 3.6 22 40 500 1000 15 25 40 V mA mA A A mA mA A PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
0.7VDD - - - - 13 140 1
HIGH level output current; WP2; note 4 VDD = 3 V; VOH = VDD - 0.4 V 2 LOW level output current; OD8 and S8; VDD = 3 V; VOL = 0.4 V note 4 LOW level output current; TS4 and OD4; note 4 LOW level output current; WP2; note 4 input capacitance; note 5 61 VDD = 3 V; VOL = 0.4 V VDD = 3 V; VOL = 0.4 V 8 4 2 -
1996 Dec 11
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
SYMBOL RUP RUP2 RUP3 RSTIN Notes
PARAMETER pull-up resistor UP; note 6a pull-up resistor UP2; note 6b pull-up resistor UP3; note 6c RESETIN resistor
CONDITIONS 8
MIN. 16 70 15
TYP. 26 15 100 31
MAX. 60 30 500 120
UNIT k k k k
1. The operating supply current through VDD1, VDD2 and VDD3 is measured with all output pins disconnected; RESETIN = RESET = HALT = 0; A23 to A0 = VDD; D15 to D0 = VDD. 2. Idle and Standby current: a) The Idle supply current through VDD1, VDD2 and VDD3 is measured with all port pins disconnected; A23 to A0 = VDD; D15 to D0 = VDD; the circuit is executing NOP instructions from an external memory. b) The Standby current through VDD1, VDD2 and VDD3 is measured with all port pins disconnected; A23 to A0 = VDD; D15 to D0 = VDD; 3. The Power-down current through VDD1, VDD2 and VDD3 is measured with all output pins disconnected; XTAL1 = RESET = HALTN = VDD; A23 to A0 = VDD; D15 to D0 = VDD; RESETIN = VSS. 4. See Table 95 for the different types. 5. Not tested in production. 6. Pull-ups: a) These pull-ups are only present on the emulation pins PHALT and NMINE. b) These active pull-ups are active on all WP2 WP4 port pins for output voltages greater than Vdd/2. They are only active during the reset sequence on the pins CS0, CS1, R/W, CSBT and FETCH for test purpose. c) These active pull-ups are only active on D15 to D0 and A23 to A0 pins when BPE is set in the SYSCON register.
1996 Dec 11
62
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
20 ADC CHARACTERISTICS VDD = 2.7 to 3.6 V; Vref(A) = VDDA = VDD; VSSA = VSS; VSS = 0 V; FCLK2 = 250 kHz to 2 MHz; Tamb = -40 to +85 C; for ADC test conditions see note 1; all voltages with respect to VSS unless otherwise specified. SYMBOL VDDA Vref(A) VSSA VIN(A) IDDA IDD(PD)(A) RVref CIA IIA FCLK2 tADS tADC Ae OSe ILe DLe Mctc Notes 1. ADC test conditions: VDD = 2.7 V, Vref(A) = 2.7 V, CLK = 20 MHz, FCLK2 = 2 MHz. 2. This resistor is switched off during Power-down mode and when the ADC is switched off (EADC = 0). 3. Parameter not measured in production, only verified on sampling basis. 4. See Fig.17 for specific FCLK2 range as function of VDD. 5. Absolute voltage error: the maximum difference between actual and ideal code transitions. Absolute voltage error accounts for all deviations of an actual converter from an ideal converter. 6. Offset error: the difference between the actual and ideal input voltage corresponding to the first actual code transition. 7. Integral non-linearity: the maximum deviation between the edges of the steps of the transfer curve and the edges of the steps of the ideal curve. The ideal step curve follows the line of least squares. 8. Differential non-linearity: the maximum deviation of the actual code width from the average code width. 9. Channel-to-channel matching: The difference between corresponding code transitions of actual characteristics taken from different channels under the same temperature, voltage and frequency conditions. PARAMETER analog supply voltage analog reference voltage analog ground analog input voltage supply current operating analog supply current Power-down mode analog input capacitance input leakage current ADC clock frequency; sampling time total conversion time absolute voltage error offset error integral non-linearity differential non-linearity channel-to-channel matching note 1 and 5 note 1 and 6 note 1 and 7 note 1 and 8 note 3 and 9 VDDA = 3.0 V VDDA = 3.0 V CONDITIONS MIN. VDD - 0.2 VDD - 0.2 VSS - 0.2 0 - - 20 - - 0.25 - - - - - - - - - - - 150 0.1 34 - - - 6 x tFCLK2 - - - - - TYP. MAX. VDD + 0.2 VDD + 0.2 VSS + 0.2 Vref(A) 250 5 150 12 1 2 - 1 1 1 1 1 UNIT V V V V A A k pF A MHz s s LSB LSB LSB LSB LSB
resistor between Vref(A) and VSSA note 2 note 3 VDDA = 3.0 V VDDA = 2.7 V; note 4
24 x tFCLK2 -
1996 Dec 11
63
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
handbook, full pagewidth
255 254 253 252 251 250
(2)
(4)
code out (1)
5 4 3 2 1 0
(3) 1 LSB (ideal)
1 2 3 4 5 6 7 250 251 252 253 254 255
AVIN (LSB ideal ) zero offset error (1) (2) (3) (4) Example of an actual transfer curve. The ideal transfer curve. Differential non-linearity. Absolute voltage error.
MGC758
V ref(A) - V SSA 1 LSB = ---------------------------------256
Fig.16 ADC conversion characteristics.
3 FCLK2 (MHz)
MGD774
2
1
0.25 0 2 2.7 3 3.6 VDD(V) 4
Fig.17 ADC clock (FCLK2) frequency range as a function of VDD. 1996 Dec 11 64
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
21 AC CHARACTERISTICS VSS = 0 V; Tamb = -40 to +85 C; tCLK = CPU clock cycle time; no fast bus cycle (FBC = 0); no wait status; all voltages with respect to VSS unless otherwise specified. SYMBOL tAVSL tSL tSHAZ tASCSL tASCSH tSLSH tDSL tAVRL tCLSL tDOSL tSHDO tHRPW tASLDTA tASHDTA tDCLDI tDATSETUP tSHDI tSHRH tSHAH tSHAWH tSHW PARAMETER address valid to AS LOW AS/DS LOW level AS HIGH to address invalid AS/DS to CS LOW AS/DS to CS HIGH AS LOW to DS LOW (write) DS LOW level (write) address valid to R/W LOW (write) R/W LOW to DS LOW (write) DATA-OUT valid to DS LOW (write) AS HIGH to DATA-OUT invalid HALT/RESET pulse width AS LOW to DTACK LOW AS HIGH to DTACK HIGH DTACK LOW to DATA-IN (set-up time) AS LOW to DATA-IN (set-up time) AS HIGH to DATA invalid (hold time) AS HIGH to R/W HIGH (write) AS HIGH to A0 HIGH AS HIGH to A0 (first byte of word cycle in 8-bit mode) LDS HIGH level before write MIN. 0.5tCLK - 10 2.5tCLK - 10 0.5tCLK - 10 -5 -5 tCLK - 15 1.5tCLK - 10 tCLK - 5 tCLK - 10 0.5tCLK - 10 0.5tCLK - 10 24tCLK - - - 0 0.5tCLK - 5 tCLK - 10 0.5tCLK - 10 2.5tCLK - 5 TYP. 0.5tCLK + 2 2.5tCLK + 2 0.5tCLK 1 1 tCLK 1.5tCLK + 2 tCLK tCLK - 2 0.5tCLK - 1 0.5tCLK - 3 - 1.5tCLK - 28 2.5tCLK - 25 tCLK 2.5tCLK - 25 0 0.5tCLK - 2 tCLK + 3 - 2.5tCLK - 2 - - - 5 5 tCLK + 15 - - - - - - 1.5tclk - 10 2.5tclk tCLK + 10 2.5tCLK - 20 - - tCLK + 10 0.5tCLK +10 - MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
handbook, halfpage
0.7 VDD
0.7 VDD
0.9 VDD test points 0.4 VDD 0.3 VDD 0.3 VDD
MLA586
Fig.18 AC testing input waveform.
1996 Dec 11
65
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
handbook, 4 columns
500 A
ITL
MGC759
-I L
100 A
IIL 1/2VDD VDD
Fig.19 Input current.
22 8051 BUS TIMING VDD = 2.7 V to 3.6 V; VSS = 0 V; Tamb = -40 to +85 C; tCLK = CPU clock cycle time; all voltages with respect to VSS unless otherwise specified. These AC parameters are not tested in production. SYMBOL tRR tWW tAL tLA tRD tDFR tLD tLW tDW tWD tWHLH PARAMETER read pulse duration write pulse duration address set-up time address hold time RD to valid data input data float after read ALE to valid data input ALE to RD WR data set-up time before WR data hold time after WR RD WR HIGH to ALE HIGH MIN. 4.5tCLK - 10 4.5tCLK - 10 1.5tCLK - 20 tCLK - 5 - - - 3tCLK - 20 6.5tCLK - 20 0.5tCLK - 10 tCLK - 10 MAX. 4.5tCLK + 10 4.5tCLK + 10 - - 3.5tCLK - 15 2tCLK - 10 6tCLK - 20 3tCLK + 20 - - tCLK + 10 ns ns ns ns ns ns ns ns ns ns ns UNIT
1996 Dec 11
66
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
23 TIMING DIAGRAMS
P90CL301BFH (C100)
book, full pagewidth
t XTAL1
CLK
t ALE
LW
t
WW
WR
tAL tLA t DW
A7 to A0
AD7 to AD0
data out
A15 to A8
AD15 to AD8
t
WD
MBG335
Fig.20 Write to 8051-compatible peripheral circuits.
handbook, full pagewidth
t tAL ALE
LD
t
WHLH
t
LW
t
RR
RD
t
LA
t
RD data in t DFR
MBG336
AD7 to AD0
AD7 to AD0
Fig.21 Read from 8051-compatible peripheral circuits.
1996 Dec 11
67
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
handbook, full pagewidth
A7 to A1 A23 to A8
tAVSL tSL
tSHAZ
AS tSHAZ tASCSL CS tASCSH
LDS UDS
tSHRH R/W
HALT RESET tHRPW tASHDTA
DTACK tASLDTA tSHDI
DATA IN
tDCLDI tDATSETUP
MGD775
Fig.22 Read cycle timing 16-bit mode.
1996 Dec 11
68
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
handbook, full pagewidth
A7 to A1 A23 to A8
tAVSL tSL
tSHAZ
AS
tSHAZ
tASCSL
tASCSH
CS tSHW tSLSH LDS UDS tAVRL tCLSL tDSL
R/W
tDOSL
tSHDO
DATA OUT
HALT RESET tHRPW tASHDTA
DTACK tASLDTA
MGD776
Fig.23 Write cycle timing 16-bit mode.
1996 Dec 11
69
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
handbook, full pagewidth
A7 to A1 A23 to A8 tAVSL tSL AS/LDS tSHAZ tASCSL CS tASCSH
tSHAWH
tSHAH
A0
R/W
tDATSETUP
tSHDI
DATA IN
tASHDTA
DTACK tASLDTA (no fast bus cycle, FBC = 0)
MGD777
Fig.24 Read cycle timing 8-bit mode.
1996 Dec 11
70
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
handbook, full pagewidth
T1 S0 CLK tCLK S1 S2
T2 S3 SB
T3 SB S4
T3 S5 S0
T1 S1 S2
T2 S3 SB
T3 SB S4
T3 S5 S0
T1 S1
A7 to A1 A23 to A8 tAVSL tSL AS
tSHAZ
tASCSL
tASCSH
CS
tSLSH tDSL LDS tAVRL tSHAWH tSHAH
A0
tCLSL
R/W tDOSL
tSHDO
DATA OUT
tASHDTA
DTACK tASLDTA
(no fast bus cycle, FBC = 0) word transfer
MGD778
Fig.25 Write cycle timing 8-bit mode clock timing.
1996 Dec 11
71
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
24 CLOCK TIMING Table 93 P90CL301BFH clock timing VDD = 2.7 V. SYMBOL fXTAL1 tCLK tCL tCH tCR tCF t CH ---------t CLK cycle time pulse width LOW pulse width HIGH rise time fall time duty cycle PARAMETER input frequency 0 37 13 13 - - 45 MIN.
P90CL301BFH (C100)
MAX. 27 - - - 5 5 55 ns ns ns ns ns %
UNIT MHz
handbook, halfpage
tCH
tCLK tCL
0.8 VDD 0.7 V tCR tCF
MBG341
Fig.26 P90CL301BFH clock timing.
1996 Dec 11
72
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
25 PIN STATES IN VARIOUS MODES
P90CL301BFH (C100)
Table 94 describes the function, I/O, type and state in various modes - RESET, Power-down, HALT, ONCE and BPE (Bus Pull-up Enable) - of the pins. Table 94 Pin states in various modes PIN A22 to A19 PCS0 to PCS3 A18 to A1 AD7 to AD1 D7 to D0 D15 to D8 PL7 to PL0 AS LDS UDS A0 AD0 R/W TROM DTACK RESET RESETIN HALT BSIZE NMIACK SP0 RX1 INT0 SP1 TX1 INT1 CLK0 SP2 RX0 INT2 CP2 SP3 TX0 1996 Dec 11 address bus 8051 chip-select address bus 8051 data bus lower 8-bits of data bus upper 8-bits of data bus port PL address strobe low data strobe upper data strobe address 0 8051 address/data 0 read write strobe Test-ROM mode data transfer acknowledgement CPU peripheral reset peripheral reset output external power-on-reset reset input; HALT input peripheral reset; fault output data bus size emulation NMIN acknowledgement second port pin 0 UART1 receive interrupt input 0 second port pin 1 UART1 transmit interrupt input 1 external clock Timer 0 second port pin 2 UART0 receive interrupt input 2 timer capture 2 second port pin 3 UART0 transmit FUNCTION I/O(1) O O O I/O I/O I/O I/O O O O O I/O O I I I OD I I OD I OD I/O I/O I I/O O I I I/O I/O I I I/O I/O 73 TYPE(2) RESET TSW4 TS4 TSW4 TSW4 TSW4 TSW4 WP4 TS4 TS4 TS4 TSW4 TSW4 TS4 UP2 N N OD8 RS N OD8 N OD8 WP2 WP2 N WP2 WP2 N N WP2 N N N WP2 WP2 Z - Z - Z Z - H H H H - Z - - - L - - L - Z W - - W - - - W - - - W - STATE(3) BPE ON PD HALT Z H Z Z Z W S H H H H - H - - - Z - - Z - Z S S - S S - - S - - - S S Z Z Z Z Z Z W Z Z Z Z Z Z - - - Z - - Z - Z W W - W W - - W - - - W W ONCE Z - Z - Z Z W Z Z Z Z Z Z - - - Z - - Z - Z W W - W W - - W - - - W W W W W W W W W - - W W W - - - - - - - - - - - - - - - - - - - - - - -
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
PIN INT3 CP3 SP4 INT4 CP4 SP5 INT5 CP5 SP6 INT6 CLK1 NMIN SP7 P8 PWM0 CP0 P9 PWM1 CP1 XTAL1 CS1 to CS0 FC1 to FC0 TSM1 to TSM0 CS2 CS3 ALE CS4 RD CS5 WR P10 SCL P11 SDA CS6 A23 CSBT ONCE P15 to P12 1996 Dec 11
FUNCTION interrupt input 3 timer capture 3 second port pin 4 interrupt input 4 timer capture 4 second port pin 5 interrupt input 5 timer capture 5 second port pin 6 interrupt input 6 external clock Timer 1 non-maskable interrupt second port pin 7 port PH pin 8 PWM output 0 timer capture 0 port PH pin 9 PWM output 1 timer capture 1 external crystal input chip-select 1 to 0 function code test mode inputs multiplexed with CS1N/0N for test purpose only. chip-select 2 chip-select 3 8051 address strobe chip-select 4 8051 read strobe chip-select 5 8051 write strobe port PH pin 10 I2C-bus I2C-bus clock data port PH pin 11 chip-select 6 address pin 23 chip-select boot ONCE mode port PH pins 15 to 12
I/O(1) I I I/O I I I/O I I I/O I I I I/O I/O O I I/O O I I O O I O O O O O O O I/O OD I/O OD O O O I I/O 74
TYPE(2) RESET N N WP2 N N WP2 N N WP2 N N N WP2 WP2 WP2 N WP2 WP2 N XI TS4 TS4 UP2 TS4 TS4 TS4 TS4 TS4 TS4 TS4 OD8 OD8 OD8 OD8 TS4 TS4 TS4 UP2 WP2 - - W - - W - - W - - - W W - - W - - - W - - H H - H - H - Z - Z - - H W - W
STATE(3) BPE ON PD HALT - - S - - S - - S - - - S S H - S H - - H S - H H H H H H H Z Z Z Z H S H - W - - W - - W - - W - - - W W W - W W - - Z Z - Z Z Z Z Z Z Z Z Z Z Z Z Z Z - Z ONCE - - W - - W - - W - - - W W W - W W - - Z Z - Z Z Z Z Z Z Z Z Z Z Z Z Z Z - Z - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
PIN ADC3 to ADC0 Vref(A) FETCH(4) EMUL(4) NMINE(4) CLKOUT(4) PHALT(4)
FUNCTION analog inputs 3 to 0 ADC reference voltage fetch output emulation mode emulation NMIN emulation clock output emulation HALT
I/O(1) I I O I I O I
TYPE(2) RESET AN AREF TS4 UP2 UP S4 UP - Z W - - S -
STATE(3) BPE ON PD HALT - Z Z - - S - - R Z - - S - ONCE - R Z - - S - - - - - - - -
Notes to the pin states in various modes 1. I = input; O = output; I/O = bidirectional. 2. See Table 95 for pin type description. 3. State of the pin in different modes RESET, PD (Power-down), HALT, ONCE and BPE (Bus Pull-up Enable). a) - = not available. b) Z = 3-state. c) W = weak pull-up. d) S = state logic 0 or logic 1. e) R = resistive f) H = HIGH state. g) L = LOW state. 4. Emulation version only. Table 95 Pin type description PIN TYPE TS4 TSW4 WP2 WP4 N UP UP2 OD8 AN S4 RS AREF 3-state output, normal input 3-state output, normal input with internal pull-up weak pull-up output, normal input weak pull-up output, normal input normal input input with internal pull-up input with internal pull-up open drain analog input strong output Schmitt trigger input analog reference input DESCRIPTION MAXIMUM LOAD (pF) 100 100 80 80 - - - 400 - 100 - -
1996 Dec 11
75
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
26 INSTRUCTION SET AND ADDRESSING MODES
P90CL301BFH (C100)
The P90CL301BFH is completely code compatible with the 68000, which means that programs developed for the 68000 will run on the P90CL301BFH. This applies to both the source and object codes. The instruction set was designed to minimize the number of mnemonics that the programmer has to remember. Following tables give an overview of the instruction set and the different addressing modes. Table 96 Instruction set; for Condition codes see notes 1 to 7 CONDITION CODES XNZ ABCD ADD ADDA ADDI ADDQ ADDX AND ANDI ASL, ASR BCC BCHG Add Decimal with Extend Add Binary Add Address Add Immediate Add Quick Add Extended AND Logical AND Immediate Arithmetic Shift Branch Conditionally Test a Bit and Change (Destination)10 + (Source)10 + X Destination (Destination) + (Source) Destination (Destination) + (Source) Destination (Destination) + Immediate Data Destination (Destination) + Immediate Data Destination (Destination) + (Source) + X Destination (Destination) (Source) Destination (Destination) Immediate Data Destination (Destination) Shifted by Destination If CC then PC + d PC ~(< bit number >) of Destination Z ~(< bit number >) of Destination < bit number > of Destination BCLR BRA BSET Test a Bit and Clear Branch Always Test a Bit and Set ~(< bit number >) of Destination Z PC + d PC ~(< bit number >) of Destination Z 1 < bit number > of Destination BSR BTST CHK CLR CMP CMPA CMPI CMPM DBcc DIVS DIVU EOR EORI EXG 1996 Dec 11 Branch to Subroutine Test a Bit Check Register against Bounds Clear an Operand Compare Compare Address Compare Immediate Compare Memory Test Condition, Decrement & Branch Signed Divide Unsigned Divide Exclusive OR Logical Exclusive OR Immediate Exchange Register PC SP @ -; PC + d PC ~(< bit number >) of Destination Z If Dn < 0 or Dn > (< source >) then TRAP 0 Destination (Destination) - (Source) (Destination) - (Source) (Destination) - Immediate Data (Destination) - (Source) If (not CC) then Dn - 1 Dn; if Dn -1 then PC + d PC (Destination) / (Source) Destination (Destination) / (Source) Destination (Destination) (Source) Destination (Destination) Immediate Data Destination Rx Ry 76 - - - - - - - - - - - - - - - - * 0 * * * * - * * * * - - * - - - - - - - - - - * - * - - - - - - * * - * * * - - * - - U* * - * * * * * * - - * - * * * * * * - * VC U* * - * * * 0 0 * - - * - * * * 0 0 * - -
MNEMONIC
DESCRIPTION
OPERATION
UUU 1 * * * * - * * * * - 0 * * * * - * * 0 0 - 0 * * * * - 0 0 0 0 -
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
MNEMONIC EXT JMP JSR LEA LINK LSL, LSR MOVE MOVE to CCR MOVE to SR
DESCRIPTION Sign Extend Jump Jump to Subroutine Load Effective Address Link and Allocate Logical Shift Move Data from Source to Destination Move to Condition Code Move to the Status Register
OPERATION (Destination) Sign - extended Destination Destination PC PC SP @ -; Destination PC Destination An An SP @ -; SP An; SP + d SP (Destination) Shifted by < count > Destination (Source) Destination (Source) CCR (Source) SR SR Destination USP An; An USP (Source) Destination Registers Destination; (Source) Registers (Source) Destination Immediate Data Destination (Destination) * (Source) Destination (Destination) * (Source) Destination 0 - (Destination)10 - X Destination 0 - (Destination) Destination 0 - (Destination) - X Destination - ~(Destination) Destination (Destination) (Source) Destination (Destination) Immediate Data Destination Destination SP @ - - (Destination) Rotated by < count > Destination (Destination) Rotated by < count > Destination SP @ + SR; SP @ + PC SP @ + CC; SP @ + PC SP @ + PC (Destination)10 - (Source)10 - X Destination - - - - - * - * * - - - - - - - - * * * - - - - - - - * * * - * -
CONDITION CODES XNZ * - - - - * * * * - - - - - * * * * - - - - * * * * - - - - - * * * VC 0 - - - - 0 0 * * - - - - - 0 * * 0 - - - - * 0 * * - - - - - 0 0 0
MOVE from SR Move from the Status Register MOVE USP MOVEA MOVEM MOVEP MOVEQ MULS MULU NBCD NEG NEGX NOP NOT OR ORI PEA RESET ROL, ROR ROXL, ROXR RTE RTR RTS SBCD SCC Move User Stack Pointer Move Address Move Multiple Registers Move Peripheral Data Move Quick Signed Multiply Unsigned Multiply Negate Decimal with Extend Negate Negate with Extend No Operation Logical Complement Inclusive OR Logical Inclusive OR Immediate Push Effective Address Reset External Devices Rotate (Without Extend) Rotate with Extend Return from Exception Return and Restore Condition Codes Return from Subroutine Subtract Decimal with Extend
U* * * - * * * - - * * * * - * * - * * * - - * * * * -
U* * * - 0 0 0 - - 0 0 * * - * * - 0 0 0 - - * * * * -
U* - -
U* - -
Set According to Condition if CC then 1 Destination; else 0 Destination
1996 Dec 11
77
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
P90CL301BFH (C100)
MNEMONIC STOP SUB SUBA SUBI SUBQ SUBX SWAP TAS TRAP TRAPV TST UNLK Notes 1. [ ] = bit number. 2. * = affected. 3. - = unaffected. 4. 0 = cleared. 5. 1 = set. 6. U = defined.
DESCRIPTION Load Status Register and Stop Subtract Binary Subtract Address Subtract Immediate Subtract Quick Subtract with Extend Swap Register Halves Test and Set an Operand Trap Trap on Overflow Test and Operand Unlink
OPERATION Immediate Data SR; STOP (Destination) - (Source) Destination (Destination) - (Source) Destination (Destination) - Immediate Data Destination (Destination) - Immediate Data Destination (Destination) - (Source) - X Destination Register [ 31:16 ] Register [ 15:0 ] (Destination) Tested CC; 1 [ 7 ] of Destination PC SSP @ -; SR SSP @ -; (Vector) PC If V then TRAP (Destination) Tested CC An SP; SP @ + An * * - * * * - - - - - -
CONDITION CODES XNZ * * - * * * * * - - * - * * - * * * * * - - * - VC * * - * * * 0 0 - - 0 - * * - * * * 0 0 - - 0 -
7. @ = location addressed by.
1996 Dec 11
78
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
26.1 Addressing modes
P90CL301BFH (C100)
Table 97 Data addressing modes; see notes 1 to 14 MODE Register Direct Addressing Data Register Direct Address Register Direct Absolute Data Addressing Absolute Short Absolute Long Program Counter Relative Addressing Relative with Offset Relative with Index and Offset Register Indirect Addressing Register Indirect Postincrement Register Indirect Predecrement Register Indirect Register Indirect with Offset Indexed Register Indirect with Offset Immediate Data Addressing Immediate Quick Immediate Implied Addressing Implied Register Notes 1. EA = Effective Address. 2. An = Address Register. 3. Dn = Data Register. 4. Xn = Address or Data Register used as Index Register. 5. N = 1 for bytes; 2 for words; 4 for long words. 6. = Replaces. 7. SR = Status Register. 8. PC = Program Counter. 9. () = Contents of. 10. d8 = 8-bit offset (displacement). 11. d16 = 16-bit offset (displacement). 12. SP = Stack Pointer. 13. SSP = System Stack Pointer. 14. USP = User Stack Pointer. EA = SR, USP, SSP, PC, SP DATA = Next Word(s) Inherent Data EA = (An) EA = (An), An An + N An An - N, EA = (An) EA = (An) + d16 EA = (An) + (Xn) + d8 EA = (PC) + d16 EA = (PC) + (Xn) + d8 EA = (Next Words) EA = (Next Two Words) EA = Dn EA = An GENERATION
1996 Dec 11
79
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
27 INSTRUCTION TIMING
P90CL301BFH (C100)
In the Tables 98 to 110 the number of bus read and write cycles are shown in parentheses as (R/W). The timing is given for operation in 16-bit mode. For operation in 8-bit mode the numbers shown in parentheses should be multiplied by a factor 2. Table 98 Effective address calculation times INSTRUCTION Rn (An) (An)+ -(An) d(An) d(An, Xi) xxx.S xxx.L d(PC) d(PC, Xi) #xxx ADDRESSING MODE Data or Address Register Direct Address Register Indirect Address Register Indirect postincrement Address Register Indirect predecrement Address Register Indirect Displacement Address Register Indirect with Index Absolute Short Absolute Long Program Counter with Displacement Program Counter with Index Immediate BYTE; WORD 0 (0/0) 4 (1/0) 4 (1/0) 7 (1/0) 11 (2/0) 14 (2/0) 8 (2/0) 12 (3/0) 11 (2/0) 14 (2/0) 4 (1/0) LONG 0 (0/0) 8 (2/0) 8 (2/0) 11 (2/0) 12 (3/0) 8 (3/0) 12 (3/0) 16 (4/0) 15 (3/0) 16 (4/0) 8 (2/0)
Table 99 MOVE Byte and MOVE Word Instruction clock periods INSTR. Rn (An) (An)+ -(An) d(An) d(An, Xi) xxx.S xxx.L d(PC) d(PC, Xi) #xxx Rn 7 (1/0) 11 (2/0) 11 (2/0) 14 (2/0) 18 (3/0) 21 (3/0) 15 (3/0) 19 (4/0) 18 (3/0) 21 (3/0) 11 (3/0) (An) 11 (1/1) 15 (2/1) 15 (2/1) 18 (2/1) 22 (3/1) 25 (3/1) 19 (3/1) 23 (4/1) 22 (3/1) 25 (3/1) 15 (2/1) (An)+ 11 (1/1) 15 (2/1) 15 (2/1) 18 (2/1) 22 (3/1) 25 (3/1) 19 (3/1) 23 (4/1) 22 (3/1) 25 (3/1) 15 (2/1) -(An) 14 (1/1) 18 (2/1) 18 (2/1) 22 (2/1) 25 (2/1) 28 (3/1) 22 (3/1) 26 (4/1) 25 (3/1) 28 (3/1) 18 (2/1) d(An) 18 (1/1) 22 (2/1) 22 (2/1) 25 (2/1) 29 (2/1) 32 (3/1) 26 (3/1) 30 (4/1) 29 (3/1) 32 (3/1) 22 (2/1) d(An, Xi) 21 (1/1) 25 (2/1) 25 (2/1) 28 (2/1) 32 (2/1) 35 (3/1) 29 (3/1) 33 (4/1) 32 (3/1) 35 (3/1) 25 (2/1) xxx.S 15 (1/1) 19 (2/1) 19 (2/1) 22 (2/1) 26 (2/1) 29 (3/1) 23 (3/1) 27 (4/1) 26 (3/1) 29 (3/1) 19 (2/1) xxx.L 19 (1/1) 23 (2/1) 23 (2/1) 26 (2/1) 30 (2/1) 33 (3/1) 27 (3/1) 31 (4/1) 30 (3/1) 33 (3/1) 23 (2/1)
1996 Dec 11
80
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
Table 100 MOVE long instruction clock periods INSTR. Rn (An) (An)+ -(An) d(An) d(An, Xi) xxx.S xxx.L d(PC) d(PC, Xi) #xxx Rn 7 (1/0) 15 (2/0) 15 (3/0) 18 (3/0) 22 (4/0) 25 (4/0) 19 (4/0) 23 (5/0) 22 (4/0) 25 (4/0) 15 (3/0) (An) 15 (1/2) 23 (2/2) 23 (3/2) 26 (3/2) 30 (4/2) 33 (4/2) 27 (4/2) 31 (5/2) 30 (4/2) 33 (4/2) 23 (3/2) (An)+ 15 (1/2) 23 (2/2) 23 (3/2) 26 (3/2) 30 (4/2) 33 (4/2) 27 (4/2) 31 (5/2) 30 (4/2) 33 (4/2) 23 (3/2) -(An) 18 (1/2) 26 (2/2) 26 (3/2) 29 (3/2) 33 (4/2) 36 (4/2) 30 (4/2) 34 (5/2) 33 (4/2) 36 (4/2) 26 (3/2) d(An) 22 (2/2) 30 (4/2) 30 (4/2) 33 (4/2) 37 (5/2) 40 (5/2) 34 (5/2) 38 (6/2) 37 (5/2) 40 (5/2) 30 (4/2)
P90CL301BFH (C100)
d(An, Xi) 25 (2/2) 33 (4/2) 33 (4/2) 36 (4/2) 40 (5/2) 43 (5/2) 37 (5/2) 41 (6/2) 40 (5/2) 43 (5/2) 33 (4/2)
xxx.S 19 (2/2) 27 (4/2) 27 (4/2) 30 (4/2) 34 (5/2) 37 (5/2) 31 (5/2) 35 (6/2) 34 (5/2) 37 (5/2) 27 (4/2)
xxx.L 23 (3/2) 31 (5/2) 31 (5/2) 34 (5/2) 38 (6/2) 41 (6/2) 35 (6/2) 39 (7/2) 38 (6/2)) 41 (6/2) 31 (5/2)
Table 101 Standard Instruction clock periods INSTRUCTION ADD AND CMP DIVS DIVU EOR MULS MULU OR SUB SIZE Byte, Word Long Byte, Word Long Byte, Word Long - - Byte, Word Long - - Byte, Word Long Byte, Word Long Notes 1. Add effective address calculation time. 2. Indicates maximum value. 3. The duration of the instruction is constant. op, An 7(1) (1/0) 7(1) (1/0) - - 7(1) 7(1) (1/0) (1/0) op, Dn 7(1) (1/0) 7(1) (1/0) 7(1) (1/0) 7(1) (1/0) 7(1) 7(1) 169(1)(2) 7(1) 7(1) (1/0) (1/0) (1/0) (1/0) (1/0) op, M 11(1) (1/1) 15(1) (1/2) 11(1) (1/1) 15(1) (1/2) - - - - 11(1) 15(1) (1/1) (1/2)
- - - - - - - - 7(1) (1/0) 7(1) (1/0)
130(1)(3) (1/0)
76(1)(3) (1/0) 76(1)(3) (1/0) 7(1) (1/0) 7(1) (1/0) 7(1) (1/0) 7(1) (1/0)
- - 11(1) (1/1) 15(1) (1/2) 11(1) (1/1) 15(1) (1/2)
1996 Dec 11
81
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
Table 102 Immediate instruction clock periods INSTRUCTION ADDI ADDQ ANDI CMPI EORI MOVEQ ORI SUBI SUBQ SIZE Byte, Word Long Byte, Word Long Byte, Word Long Byte, Word Long Byte, Word Long Long Byte, Word Long Byte, Word Long Byte, Word Long Note 1. Add effective address calculation time. Table 103 Shift/rotate instruction clock periods INSTRUCTION ASR, ASL LSR, LSL ROR, ROL ROXR, ROXL SIZE Byte Word Byte, Word Long Byte, Word Long Byte, Word Long Note 1. Add effective address calculation time. REGISTER 13 + 3n (1/0) 13 + 3n (1/0) 13 + 3n (1/0) 13 + 3n (1/0) 13 + 3n (1/0) 13 + 3n (1/0) 13 + 3n (1/0) 13 + 3n (1/0) op<#>, Dn 14 (2/0) 18 (3/0) 7(1) (1/0) 7(1) (1/0) 14 (2/0) 18 (3/0) 14 (2/0) 18 (3/0) 14 (2/0) - 7 (1/0) 14 (2/0) 18 (3/0) 14 (2/0) 18 (3/0) 7(1) (1/0) 7(1) (1/0)
P90CL301BFH (C100)
op<#>, An - - 7(1) (1/0) 7(1) (1/0) - - - - - - - - - - - 7 (1/0) 7 (1/0)
op<#>, M 18(1) (2/1) 26(1) (3/2) 11(1) (1/1) 15(1) (1/2) 18(1) (2/1) 26(1) (3/2) 14 (2/0) 18 (3/0) 18(1) (2/1) 26(1) (3/2) - 18(1) 26(1) (2/1) (3/2)
18(1) (2/1) 26(1) (3/2) 11(1) (1/1) 15(1) (1/2)
MEMORY 14 (1/1)(1) - 14 (1/1)(1) - 14 (1/1)(1) - 14 (1/1)(1) -
1996 Dec 11
82
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
Table 104 Single operand instruction clock periods INSTRUCTION CLR NBCD NEG NEGX NOT Scc TAS TST SIZE Byte, Word Long Byte, Word Byte, Word Long Byte, Word Long Byte, Word Long Byte, Word Long Byte Byte, Word Long Notes 1. Add effective address calculation time. 2. Subtract one read cycle (-4(1/0)) from effective address calculation. 3. Subtract two read cycles (-8(2/0)) from effective address calculation. Table 105 Bit manipulation instruction clock periods DYNAMIC INSTRUCTION BCHG BCLR BSET BTST SIZE REGISTER Byte Long Byte Long Byte Long Byte Long Note 1. Add effective address calculation time. - 10 (1/0) - 10 (1/0) - 10 (1/0) - 7 (1/0) 14 14 MEMORY 14 (1/1)(1) - (1/1)(1) - (1/1)(1) - 7 (1/0)(1) - REGISTER 7 (1/0) 7 (1/0) 10 (1/0) 7 (1/0) 7 (1/0) 7 (1/0) 7 (1/0) 7 (1/0) 7 (1/0) 13 (1/0) 13 (1/0) 10 (1/0) 7 (1/0) 7 (1/0)
P90CL301BFH (C100)
MEMORY 11 (1/1)(1)(2) 15 (1/2)(1)(3) 14 (1/1)(1) 11 (1/1)(1) 15 (1/2)(1) 11 (1/1)(1) 15 (1/2)(1) 11 (1/1)(1) 15 (1/2)(1) 17 (1/1)(1) 14 (1/1)(1) 15 (2/1)(1)(2) 7 (1/0)(1) 7 (1/0)(1)
STATIC REGISTER - 17 (2/0) - 17 (2/0) - 17 (2/0) - 14 (2/0) MEMORY 21 (2/1)(1) - 21 (2/1)(1) - 21 (2/1)(1) - 14 (2/0)(1) -
1996 Dec 11
83
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
Table 106 Conditional instruction clock periods
P90CL301BFH (C100)
TRAP OR BRANCH INSTRUCTION Bcc BRA BSR DBcc CHK TRAPV Note 1. Add effective address calculation time. Table 107 JMP, JSR, LEA, PEA, MOVEM instruction clock periods n = number of registers to move. INSTRUCTION SIZE JMP JSR LEA PEA MOVEM MR - - - - (An) 7 (1/0) 18 (1/2) 7 (1/0) 18 (1/2) - - - - 26+7n (2+n/0) (An)+ -(An) - - - - - d(An) 14 (2/0) 25 (2/2) 14 (2/0) 25 (2/2) 30+7n (3+n/0) d(An, Xi) 17 (2/0) 28 (2/2) 17 (2/0) 28 (2/2) 33+7n (3+n/0) xxx.S 14 (2/0) 25 (2/2) 14 (2/0) 25 (2/2) 30+7n (3+n/0) xxx.L 18 (3/0) 28 (2/2) 18 (3/0) 28 (2/2) 34+7n (4+n/0) d(PC) 14 (2/0) 25 (2/2) 14 (2/0) 25 (2/2) 30+7n (3+n/0) d(PC, Xi) 17 (2/0) 28 (2/2) 17 (2/0) 28 (2/2) 33+7n (3+n/0) DISPLAY TAKEN Byte Word Byte Word Byte Word cc True cc False - - 13 (1/0) 14 (2/0) 13 (1/0) 14 (2/0) 21 (1/2) 22 (2/2) - 17 (2/0) 70 (3/4)(1) 55 (3/4) NOT TAKEN 13 (1/0) 14 (2/0) - - - - 14 (2/0) 17 (3/2) 19 (1/0)(1) 10 (1/0)
Word 26+7n (2+n/0)
Long 26+11n 26+11n - (2+2n/0) (2+2n/0) MOVEM RM Word 23+7n (2/n) Long 23+11n (2/2n) - - 23+7n (2/n)
30+11n 33+11n (3+2n/0) (3+2n/0) 27+7n (3/n) 30+7n (3/n) 30+11n (3/2n)
30+11n 34+11n 30+11n 33+11n (3+2n/0) (4+2n/0) (3+2n/0) (3+2n/0) 27+7n (3/n) 27+11n (3/2n) 31+7n (4/n) 31+11n (4/2n) - - - -
23+11n 27+11n (2/2n) (3/2n)
Table 108 Multi-precision Instruction Clock Periods INSTRUCTION ADDX CMPM SUBX ABCD SBCD 1996 Dec 11 Long Byte, Word Long Byte, Word Long Byte Byte SIZE Byte, Word op Dn, An 7 (1/0) 7 (1/0) - - 7 (1/0) 7 (1/0) 10 (1/0) 10 (1/0) 84 op M, M 28 (3/1) 40 (5/2) 18 (3/0) 26 (5/0) 28 (3/1) 40 (5/2) 31 (3/1) 31 (3/1)
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
Table 109 Miscellaneous Clock Periods INSTRUCTION ANDI to CCR ANDI to SR EORI to CCR EORI to SR EXG EXT LINK MOVE from SR MOVE to CCR MOVE to SR MOVE from USP MOVE to USP MOVEP NOP ORI to CCR ORI to SR RESET RTE short format RTE long format no rerun with rerun return of TAS RTR RTS STOP SWAP UNLK Note 1. Add effective address calculation time. - - - - - - - - 140 (18/0) 146 (18/0) 151 (19/0) 22 (4/0) 15 (3/0) 17 (2/0) 7 (1/0) 15 (3/0) - - - - - - - - - - - - - Word Long - - - - - - Word Long - - - - - SIZE REGISTER 14 (2/0) 14 (2/0) 14 (2/0) 14 (2/0) 13 (2/0) 7 (1/0) 7 (1/0) 25 (2/2) 7 (1/0) 10 (1/0) 10 (1/0) 7 (1/0) 7 (1/0) - - 7 (1/0) 14 (2/0) 14 (2/0) 154 (1/0) - 11 10 MEMORY - - - - - - - - (1/1)(1) (1/0)(1) - - - - - - - - -
P90CL301BFH (C100)
REGISTER TO MEMORY - - - - - - - - - - - - - 25 (2/2) 39 (2/4) - - - - - - - - - - - - -
MEMORY TO REGISTER - - - - - - - - - - - - - 22 (4/0) 36 (6/0) - - - - - - - - - - - - - -
10 (1/0)(1)
1996 Dec 11
85
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
Table 110 Exception processing clock periods EXCEPTION Address error Bus error Interrupt Illegal instruction Privilege instruction Trace Trap Divide by zero RESET(3) Notes
P90CL301BFH (C100)
NUMBER OF CLOCK PERIODS 158 (3/17) 158 (3/17) 65 (4/4)(1) 55 (3/4) 55 (3/4) 55 (3/4) 52 (3/4) 64 (3/4)(2) 43 (4/0)
1. The interrupt acknowledge bus cycle is assumed to take four external clock periods. 2. Add effective address calculation time. 3. Indicates the maximum time from when RESET and HALT are first sampled as negated to first instruction fetch.
1996 Dec 11
86
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
28 PACKAGE OUTLINE
P90CL301BFH (C100)
LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm
SOT315-1
c
y X A 60 61 41 40 Z E
e E HE wM bp 80 1 pin 1 index 20 ZD bp D HD wM B vM B vM A L 21 detail X A A2 A1
Q (A 3) Lp
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT315-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION A max. 1.6 A1 0.16 0.04 A2 1.5 1.3 A3 0.25 bp 0.25 0.13 c 0.18 0.12 D (1) 12.1 11.9 E (1) 12.1 11.9 e 0.5 HD HE L 1.0 Lp 0.7 0.3 Q 0.70 0.58 v 0.2 w 0.15 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 4 0o
o
14.15 14.15 13.85 13.85
ISSUE DATE 92-03-24 95-12-19
1996 Dec 11
87
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
29 SOLDERING 29.1 Introduction
P90CL301BFH (C100)
If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering LQFP packages LQFP48 (SOT313-2), LQFP64 (SOT314-2) or LQFP80 (SOT315-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 29.4 Repairing soldered joints
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 29.2 Reflow soldering
Reflow soldering techniques are suitable for all LQFP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 29.3 Wave soldering
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
1996 Dec 11
88
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
30 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
P90CL301BFH (C100)
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 31 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 32 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1996 Dec 11
89
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
NOTES
P90CL301BFH (C100)
1996 Dec 11
90
Philips Semiconductors
Preliminary specification
Low voltage 16-bit microcontroller
NOTES
P90CL301BFH (C100)
1996 Dec 11
91
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580/xxx France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 247 9145, Fax. +7 095 247 9144 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1, P.O. Box 22978, TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
647021/50/01/pp92
Date of release: 1996 Dec 11
Document order number:
9397 750 01261

▲Up To Search▲

Price & Availability of P90CL301

	To Download P90CL301 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .